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Journal of Micro/Nanolithography, MEMS, and MOEMS

Topology-oriented pattern extraction and classification for synthesizing lithography test patterns
Author(s): Seongbo Shim; Youngsoo Shin
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Paper Abstract

A small but diverse set of test patterns is essential for the optimization of lithography parameters. We selectively extract the complicated patterns that are likely to cause lithography defects from test layouts. These patterns are hierarchically classified into groups based on geometric similarity; then, a small number of patterns are chosen to represent each group. We demonstrate this approach in the synthesis of test patterns for metal layers. The total area of the resulting test patterns is only 10% of that of a set produced using a more conventional technique; the resulting hotspot library has 30% fewer patterns, and the time required to create it is cut by an order of magnitude.

Paper Details

Date Published: 23 January 2015
PDF: 12 pages
J. Micro/Nanolith. 14(1) 013503 doi: 10.1117/1.JMM.14.1.013503
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 14, Issue 1
Show Author Affiliations
Seongbo Shim, KAIST (Korea, Republic of)
SAMSUNG Electronics (Korea, Republic of)
Youngsoo Shin, KAIST (Korea, Republic of)


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