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Journal of Micro/Nanolithography, MEMS, and MOEMS

Triple patterning lithography layout decomposition using end-cutting<xref ref-type="fn" rid="fn1" /<
Author(s): Bei Yu; Subhendu Roy; Jhih-Rong Gao; David Z. Pan
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Paper Abstract

Triple patterning lithography (TPL) is one of the most promising techniques in the 14-nm logic node and beyond. Conventional LELELE type TPL technology suffers from native conflict and overlapping problems. Recently, as an alternative process, TPL with end-cutting (LELE-EC) was proposed to overcome the limitations of LELELE manufacturing. In the LELE-EC process, the first two masks are LELE type double patterning, while the third mask is used to generate the end-cuts. Although the layout decomposition problem for LELELE has been well studied in the literature, only a few attempts have been made to address the LELE-EC layout decomposition problem. We propose a comprehensive study for LELE-EC layout decomposition. Layout graph and end-cut graph are constructed to extract all the geometrical relationships of both input layout and end-cut candidates. Based on these graphs, integer linear programming is formulated to minimize the conflict and the stitch numbers. The experimental results demonstrate the effectiveness of the proposed algorithms.

Paper Details

Date Published: 4 November 2014
PDF: 9 pages
J. Micro/Nanolith. 14(1) 011002 doi: 10.1117/1.JMM.14.1.011002
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 14, Issue 1
Show Author Affiliations
Bei Yu, The Univ. of Texas at Austin (United States)
Subhendu Roy, The Univ. of Texas at Austin (United States)
Jhih-Rong Gao, Cadence Design Systems (United States)
David Z. Pan, The Univ. of Texas at Austin (United States)


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