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Journal of Micro/Nanolithography, MEMS, and MOEMS

Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations
Author(s): Sergio Gómez; Francesc Moll; Joan Mauricio
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Paper Abstract

A lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables the possibility to objectively compare the lithography quality of different layout design implementations. Moreover, we propose a pattern construct classifier to reduce the set of lithography simulations necessary to estimate the litho degradation. The application of the yield model is demonstrated for different layout configurations showing that a certain degree of layout regularity improves the parametric yield and increases the number of good dies per wafer.

Paper Details

Date Published: 16 September 2014
PDF: 15 pages
J. Micro/Nanolith. 13(3) 033016 doi: 10.1117/1.JMM.13.3.033016
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 13, Issue 3
Show Author Affiliations
Sergio Gómez, Univ. Politècnica de Catalunya (Spain)
Francesc Moll, Univ. Politècnica de Catalunya (Spain)
Joan Mauricio, Univ. Politècnica de Catalunya (Spain)


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