Share Email Print
cover

Journal of Micro/Nanolithography, MEMS, and MOEMS

Transistor gate line roughness formation and reduction in sub-30-nm gate patterning using multilayer hard mask structure
Author(s): Lingkuan Meng; Xiaobin He; Chunlong Li; Junjie Li; Peizhen Hong; Junfeng Li; Chao Zhao; Jiang Yan
Format Member Price Non-Member Price
PDF $20.00 $25.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

In this work, we have investigated the evolution of line roughness from the photoresist (PR) to the poly-silicon gate etch based on the composite SiO2 /Si3 N4 /SiO2 (ONO) multilayer hard mask structure using a capacitively coupled plasma etcher. A severe line roughness could be observed during gate patterning when the PR pattern was directly transferred into the ONO hard mask. Then, the formation mechanisms of line roughness were the results of the effects of decomposed oxygen radical generated from the SiO 2 mask because of ion bombardment and the rough surface morphology of poly-silicon that accelerates the etching of both the hard mask and the PR sidewalls by reflected ions. We found that a combination of an amorphous silicon (α -Si) capping layer and amorphous Si gate could effectively reduce the strong dependence of hard mask etch on PR and ions reflection effect from rough surface morphology of poly-silicon. Finally, our results have shown that the gate pattern with a fairly smooth line, without deformation, and with the gate length of 29 nm and the line width roughness of 3.4 nm can be achieved.

Paper Details

Date Published: 27 August 2014
PDF: 8 pages
J. Micro/Nanolith. 13(3) 033010 doi: 10.1117/1.JMM.13.3.033010
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 13, Issue 3
Show Author Affiliations
Lingkuan Meng, Institute of Microelectronics (China)
Xiaobin He, Institute of Microelectronics (China)
Chunlong Li, Institute of Microelectronics (China)
Junjie Li, Institute of Microelectronics (China)
Peizhen Hong, Institute of Microelectronics (China)
Junfeng Li, Institute of Microelectronics (China)
Chao Zhao, Institute of Microelectronics (China)
Jiang Yan, Institute of Microelectronics (China)


© SPIE. Terms of Use
Back to Top