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Journal of Micro/Nanolithography, MEMS, and MOEMS

Design implications of extremely restricted patterning
Author(s): Kaushik Vaidyanathan; Renzhi Liu; Lars W. Liebmann; Kafai Lai; Andrzej J. Strojwas; Larry Pileggi
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Paper Abstract

Escalating manufacturing cost and complexity is challenging the premise of affordable scaling. With lithography accounting for a large fraction of wafer costs, researchers are actively exploring several cost-effective alternative lithographic techniques, such as directed self-assembly, self-aligned multiple patterning, etc. However, most of the alternative lithographic techniques are restrictive, and it is important to understand the impact of such pattering restrictions on system-on-chip (SoC) design. To this end, we artificially restricted all layers in a 14 nm process to be pure gratings and observed that the pure gratings approach results in an inefficient SoC design with several process integration concerns. To come up with a technology definition that is mindful of designer requirements, it is essential to undertake a holistic design technology co-optimization (DTCO) considering several SoC design elements, such as standard cell logic, static random access memory bitcells, analog blocks, and physical synthesis. Our DTCO on the IBM 14 nm process with additional 10- and 7-nm node-like pattern restrictions leads us to converge on a set of critical pattern constructs that are required for an efficient and affordable SoC design.

Paper Details

Date Published: 3 October 2014
PDF: 13 pages
J. Micro/Nanolith. 13(3) 031309 doi: 10.1117/1.JMM.13.3.031309
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 13, Issue 3
Show Author Affiliations
Kaushik Vaidyanathan, Carnegie Mellon Univ. (United States)
Renzhi Liu, Carnegie Mellon Univ. (United States)
Lars W. Liebmann, IBM Corp. (United States)
Kafai Lai, IBM Corp. (United States)
Andrzej J. Strojwas, Carnegie Mellon Univ. (United States)
Larry Pileggi, Carnegie Mellon Univ. (United States)


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