Share Email Print
cover

Journal of Micro/Nanolithography, MEMS, and MOEMS

Metrology needs for through-silicon via fabrication
Author(s): Victor H. Vartanian; Richard A. Allen; Larry Smith; Klaus Hummler; Steve Olson; Brian C. Sapp
Format Member Price Non-Member Price
PDF $20.00 $25.00

Paper Abstract

This paper focuses on the metrology needs and challenges of through-silicon via (TSV) fabrication, consisting of TSV etch, liner, barrier, and seed (L/B/S) depositions, copper plating, and copper chemical mechanical planarization. These TSVs, with typical dimensions within a factor of two or so of ≈5  μm  ×50  μm (diameter×depth ), present an innovative set of metrology challenges because of the high aspect ratio and large feature sizes. The metallization deposition process includes thin layers of L/B/S metal; metrology for these layers determines whether there is complete coverage of the sidewalls. Metrology for the fill step includes verifying that the TSVs are deposited without voids and that the extent of stress on the surrounding silicon does not exceed acceptable limits.

Paper Details

Date Published: 27 February 2014
PDF: 10 pages
J. Micro/Nanolith. 13(1) 011206 doi: 10.1117/1.JMM.13.1.011206
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 13, Issue 1
Show Author Affiliations
Victor H. Vartanian, SEMATECH Inc. (United States)
Richard A. Allen, National Institute of Standards and Technology (United States)
Larry Smith, SEMATECH Inc. (United States)
Klaus Hummler, SEMATECH Inc. (United States)
Steve Olson, SEMATECH Inc. (United States)
Brian C. Sapp, SEMATECH Inc. (United States)


© SPIE. Terms of Use
Back to Top