Share Email Print
cover

Journal of Micro/Nanolithography, MEMS, and MOEMS • Open Access

Special Section Guest Editorial: Metrology and Inspection for 3-D Integrated Circuits and Interconnects

Paper Abstract

Three-dimensional integration of stacked device cells in front end (FE) and of advanced metallization in back end (BE) enabled by through-silicon via (TSV) opens new paths to increased product functionality even without device shrink. But “going 3-D” also creates many new challenges for the semiconductor industry. Development of the new designs, manufacturing methods, and processes demands rapid technology and materials characterization, as well as in-line metrology and inspection for process development and control in completely new and changing applications environments.

Paper Details

Date Published: 25 March 2014
PDF: 2 pages
J. Micro/Nanolith. 13(1) 011201 doi: 10.1117/1.JMM.13.1.011201
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 13, Issue 1
Show Author Affiliations
Alexander Starikov, Consultant (United States)
Yi-Sha Ku, Industrial Technology Research Institute (Taiwan)


© SPIE. Terms of Use
Back to Top