Share Email Print
cover

Journal of Micro/Nanolithography, MEMS, and MOEMS

Sidewall profile engineering for the reduction of cut exposures in self-aligned pitch division patterning
Author(s): Frederick T. Chen; Wei-Su Chen; Ming-Jinn Tsai; Tzu-Kun Ku
Format Member Price Non-Member Price
PDF $20.00 $25.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

As 193-nm immersion lithography will likely be required to be extended beyond 40-nm half-pitch, multiple patterning lithography will become a necessity in that scenario. We present a cost-effective approach for double patterning with extendibility to sub-10-nm half-pitch division, which is a very promising candidate for advanced logic nodes. Spacers on sufficiently sloped sidewalls directly transferred from a low-contrast photoresist profile can be removed by anisotropic etching. Alternatively, spacer gaps for defining trenches may be prevented from penetrating to the substrate by the use of sloped sidewalls. These sloped sidewalls are defined by attenuated phase-shift mask features, which impart phase shifts other than 180 deg or 0 deg. Loop trimming and sidewall spacer definition are accomplished in a single photomask. In addition, there is now an extra ability to define random, arbitrary breaks in the spacer-defined pattern, without using an extra exposure for specified cuts. In this way, a single exposure using a modified attenuated phase-shift photomask, followed by a low-contrast development process around the sensitivity limit, is sufficient to pattern regularly arranged spacer-defined lines at fixed pitch while including some predetermined line cut locations.

Paper Details

Date Published: 25 March 2014
PDF: 13 pages
J. Micro/Nanolith. 13(1) 011008 doi: 10.1117/1.JMM.13.1.011008
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 13, Issue 1
Show Author Affiliations
Frederick T. Chen, Industrial Technology Research Institute (Taiwan)
Wei-Su Chen, Industrial Technology Research Institute (Taiwan)
Ming-Jinn Tsai, Industrial Technology Research Institute (Taiwan)
Tzu-Kun Ku, Industrial Technology Research Institute (Taiwan)


© SPIE. Terms of Use
Back to Top