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Journal of Micro/Nanolithography, MEMS, and MOEMS

Double patterning with dual hard mask for 28-nm node devices and below
Author(s): Hubert Hody; Vasile Paraschiv; Emma Vecchio; Sabrina Locorotondo; Gustaf Winroth; Raja Athimulam; Werner Boullart
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Paper Abstract

A double patterning process resulting in amorphous silicon (a-Si) gate lines with a thickness of 80 nm and a lateral critical dimension <30  nm is reported. A full stack for a double patterning approach for etch transfer down to an Si layer, including a hard mask (HM) in which the line and cut patterning are performed, is presented. The importance of the HM in the success or failure of the exercise is evidenced. Once the suitable HM has been selected, the etch chemistry is shown to have a significant impact on the line width roughness (LWR) of the gate. Ultimately, remarkably low LWR could be achieved on gates exhibiting a straight profile. All the results shown in this paper have been obtained on 300-mm wafers.

Paper Details

Date Published: 1 October 2013
PDF: 6 pages
J. Micro/Nanolith. 12(4) 041306 doi: 10.1117/1.JMM.12.4.041306
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 12, Issue 4
Show Author Affiliations
Hubert Hody, IMEC (Belgium)
Vasile Paraschiv, IMEC (Belgium)
Emma Vecchio, IMEC (Belgium)
Sabrina Locorotondo, IMEC (Belgium)
Gustaf Winroth, IMEC (Belgium)
Raja Athimulam, IMEC (Belgium)
Werner Boullart, IMEC (Belgium)


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