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Journal of Micro/Nanolithography, MEMS, and MOEMS • Open Access

Contact hole shrink process using graphoepitaxial directed self-assembly lithography
Author(s): Yuriko Seino; Hiroki Yonemitsu; Hironobu Sato; Masahiro Kanno; Hirokazu Kato; Katsutoshi Kobayashi; Ayako Kawanishi; Tsukasa Azuma; Makoto Muramatsu; Seiji Nagahara; Takahiro Kitano; Takayuki Toshima

Paper Abstract

A contact hole shrink process using directed self-assembly lithography (DSAL) for sub-30 nm contact hole patterning is reported on. DSAL using graphoepitaxy and poly (styrene-block-methyl methacrylate) (PS-b -PMMA) a block copolymer (BCP) was demonstrated and characteristics of our process are spin-on-carbon prepattern and wet development. Feasibility of DSAL for semiconductor device manufacturing was investigated in terms of DSAL process window. Wet development process was optimized first; then critical dimension (CD) tolerance of prepattern was evaluated from three different aspects, which are DSA hole CD, contact edge roughness (CER), and hole open yield. Within 70+/−5  nm hole prepattern CD, 99.3% hole open yield was obtained and CD tolerance was 10 nm. Matching between polymer size and prepattern size is critical, because thick PS residual layer appears at the hole bottom when the prepattern holes are too small or too large and results in missing holes after pattern transfer. We verified the DSAL process on a 300-mm wafer at target prepattern CD and succeeded in patterning sub-30 nm holes on center, middle, and edge of wafer. Average prepattern CD of 72 nm could be shrunk uniformly to DSA hole pattern of 28.5 nm. By the DSAL process, CD uniformity was greatly improved from 7.6 to 1.4 nm, and CER was also improved from 3.9 to 0.73 nm. Those values represent typical DSAL rectification characteristics and are significant for semiconductor manufacturing. It is clearly demonstrated that the contact hole shrink using DSAL is a promising patterning method for next-generation lithography.

Paper Details

Date Published: 12 August 2013
PDF: 7 pages
J. Micro/Nanolith. 12(3) 033011 doi: 10.1117/1.JMM.12.3.033011
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 12, Issue 3
Show Author Affiliations
Yuriko Seino, Toshiba Corp. (Japan)
Hiroki Yonemitsu, Toshiba Corp. (Japan)
Hironobu Sato, Toshiba Corp. (Japan)
Masahiro Kanno, Toshiba Corp. (Japan)
Hirokazu Kato, Toshiba America Electronic Components, Inc. (United States)
Katsutoshi Kobayashi, Toshiba Corp. (Japan)
Ayako Kawanishi, Toshiba Corp. (Japan)
Tsukasa Azuma, Toshiba Corp. (Japan)
Makoto Muramatsu, Tokyo Electron Kyushu Ltd. (Japan)
Seiji Nagahara, Tokyo Electron Ltd. (Japan)
Takahiro Kitano, Tokyo Electron Kyushu Ltd. (Japan)
Takayuki Toshima, Tokyo Electron Kyushu Ltd. (Japan)

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