Share Email Print
cover

Journal of Micro/Nanolithography, MEMS, and MOEMS

Methods for joint optimization of mask and design targets for improving lithographic process window
Author(s): Shayak Banerjee; Kanak B. Agarwal; Michael Orshansky
Format Member Price Non-Member Price
PDF $20.00 $25.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Low-k 1 lithography results in features that suffer from poor lithographic yield in the presence of process variation. The problem is especially pronounced for lower-level metals used for local routing, where bi-directionality and tight pitches give rise to lithography unfriendly layout patterns. However, there exists inherent unutilized flexibility in design shapes, e.g., one can modify such wires without significantly affecting design behavior. We develop two different techniques to simultaneously modify mask and design shapes during optical proximity correction (OPC) to improve lithographic yield of low-level metal layers. The methods utilize image slope information, which is available during OPC image simulations at no extra cost, as a measure of lithographic process window. We first propose a method that identifies fragments with low normalized image log slope (NILS) and then use this NILS information to guide dynamic target modification between iterations of OPC. The method uses a pre-characterized lookup table to assign a different magnitude of local target correction to different NILS bins. Next we develop an optimization flow where we derive a cost function that maximizes both contour fidelity and robustness to drive our simultaneous mask and target optimization (SMATO) method. We develop analytical equations to predict the cost for a given mask and target modification and use a fast algorithm to minimize this cost function to obtain an optimal mask and target solution. Our experiments on sample 1× (M1) layouts show that the use of SMATO reduces the process manufacturability index (PMI) by 15.4% compared with OPC, which further leads to 69% reduction in the number of layout hotspots. Additionally, such improvement is obtained at low average runtime overhead (5.5%). Compared with process window optical proximity correction (PWOPC), we observe 4.6% improvement in PMI at large (2.6× ) improvement in runtime.

Paper Details

Date Published: 11 June 2013
PDF: 16 pages
J. Micro/Nanolith. 12(2) 023014 doi: 10.1117/1.JMM.12.2.023014
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 12, Issue 2
Show Author Affiliations
Shayak Banerjee, IBM Corp. (United States)
Kanak B. Agarwal, IBM Austin Research Lab. (United States)
Michael Orshansky, The Univ. of Texas at Austin (United States)


© SPIE. Terms of Use
Back to Top