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Journal of Electronic Imaging

Field programmable gate arrays-based number plate binarization and adjustment for automatic number plate recognition systems
Author(s): Xiaojun Zhai; Faycal Bensaali; Reza Sotudeh
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Paper Abstract

Number plate (NP) binarization and adjustment are important preprocessing stages in automatic number plate recognition (ANPR) systems and are used to link the number plate localization (NPL) and character segmentation stages. Successfully linking these two stages will improve the performance of the entire ANPR system. We present two optimized low-complexity NP binarization and adjustment algorithms. Efficient area/speed architectures based on the proposed algorithms are also presented and have been successfully implemented and tested using the Mentor Graphics RC240 FPGA development board, which together require only 9% of the available on-chip resources of a Virtex-4 FPGA, run with a maximum frequency of 95.8 MHz and are capable of processing one image in 0.07 to 0.17 ms.

Paper Details

Date Published: 15 January 2013
PDF: 11 pages
J. Electron. Imag. 22(1) 013009 doi: 10.1117/1.JEI.22.1.013009
Published in: Journal of Electronic Imaging Volume 22, Issue 1
Show Author Affiliations
Xiaojun Zhai, Univ. of Hertfordshire (United Kingdom)
Faycal Bensaali
Reza Sotudeh

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