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Optical Engineering

Graphical approach for multiple values logic minimization
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Paper Abstract

Multiple valued logic (MVL) is sought for designing high complexity, highly compact, parallel digital circuits. However, the practical realization of an MVL-based system is dependent on optimization of cost, which directly affects the optical setup. We propose a minimization technique for MVL logic optimization based on graphical visualization, such as a Karnaugh map. The proposed method is utilized to solve signed-digit binary and trinary logic minimization problems. The usefulness of the minimization technique is demonstrated for the optical implementation of MVL circuits.

Paper Details

Date Published: 1 March 1999
PDF: 6 pages
Opt. Eng. 38(3) doi: 10.1117/1.602123
Published in: Optical Engineering Volume 38, Issue 3
Show Author Affiliations
Abdul Ahad Sami Awwal, Wright State Univ. (United States)
Khan M. Iftekharuddin, North Dakota State Univ. (United States)

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