Share Email Print
cover

Journal of Micro/Nanolithography, MEMS, and MOEMS

Design intent application to tolerance-based manufacturing system
Format Member Price Non-Member Price
PDF $20.00 $25.00

Paper Abstract

Continuous shrinkage of the design rule in large-scale integrated circuit devices brings about greater difficulty in the manufacturing process. The keys to meeting small process margin are adequate extraction of critical dimension tolerance for each object, considering design intent in terms of electrical behavior, and assigning the tolerance for each process step. However, once the design data are converted to layout data and signed off, most of the design intent is abandoned and unrecognized in the process phase. Thus, uniform and redundant tolerance is used, and therefore, excess tolerance is assigned for some layouts. To solve the problem described above, a tolerance-based manufacturing system utilizing flexible layout-dependent speculation derived from design intent has been discussed. Using a 40-nm node test chip, electrically critical spots, such as timing, cross-talk noise, electromigration, with small margins are extracted, assigned to the physical layout, and utilized in the manufacturing process. The flow is applicable for optical proximity effect correction (OPC) turnaround time reduction, optimization of OPC/lithography compliance check (LCC) specification, and failure-analysis acceleration. Consequently, a design-intent-aware manufacturing system is promising for realizing proper process specifications and computational cost reduction, in addition to yield enhancement.

Paper Details

Date Published: 1 January 2011
PDF: 7 pages
J. Micro/Nanolith. 10(1) 013020 doi: 10.1117/1.3565449
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 10, Issue 1
Show Author Affiliations
Sachiko Kobayashi, Toshiba Materials Co., Ltd. (Japan)
Satoshi Tanaka, Toshiba Materials Co., Ltd. (Japan)
Suigen Kyoh, Toshiba Materials Co., Ltd. (Japan)
Shimon Maeda, Toshiba Materials Co., Ltd. (Japan)
Masanari Kajiwara, Toshiba Materials Co., Ltd. (Japan)
Soichi Inoue, Toshiba Materials Co., Ltd. (Japan)
Koji Nakamae, Osaka Univ. (Japan)


© SPIE. Terms of Use
Back to Top