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Journal of Micro/Nanolithography, MEMS, and MOEMS

Electrical validation of through-process optical proximity correction verification limits
Author(s): Omprakash Jaiswal; Rakesh Kuncha; Taksh Bharat; Vipin Madangarli; Edward W. Conrad; James A. Bruce; Sajan R. Marokkey
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Paper Abstract

Electrical validation of through process optical proximity correction verification limits in 32-nm process technology is presented. Correlation plots comparing electrical and optical simulations are generated by weighting the probability of occurrence of each process conditions. The design of electrical layouts is extended to subdesign rules to force failure and derive better correlation between electrical and simulated outputs. Some of these subdesign rule designs amplify the failures induced by an exposure tool, such as optical aberrations. Observations in this regard are reported. Sensitivity with respect to dimensions, orientations, and wafer distribution are discussed in detail.

Paper Details

Date Published: 1 October 2010
PDF: 6 pages
J. Micro/Nanolith. 9(4) 041303 doi: 10.1117/1.3514703
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 9, Issue 4
Show Author Affiliations
Omprakash Jaiswal, IBM Corp. (India)
Rakesh Kuncha, IBM Corp. (India)
Taksh Bharat, IBM Corp. (India)
Vipin Madangarli, IBM Corp. (India)
Edward W. Conrad, IBM Corp. (United States)
James A. Bruce, IBM Corp. (United States)
Sajan R. Marokkey, Infineon Technologies North America Corp. (United States)

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