Share Email Print

Journal of Micro/Nanolithography, MEMS, and MOEMS

22-nm-node technology active-layer patterning for planar transistor devices
Format Member Price Non-Member Price
PDF $20.00 $25.00

Paper Abstract

As the semiconductor device size shrinks without a concomitant increase of numerical aperture (NA) and refractive index of the immersion fluid, printing 22-nm-technology devices presents challenges in resolution. Therefore, aggressive integration of a resolution enhancement technique (RET), design for manufacturability (DFM), and layer-specific lithographic process development are strongly required in 22-nm-technology lithography. We show patterning of an active layer of a 22-nm-node planar logic transistor device, and discuss achievements and challenges. Key issues identified include printing tight pitches, isolated trench, and 2-D features while maintaining a large lithographic process window across the chip while scaling down the cell size. Utilizing NA=1.2, printing of the static random access memory (SRAM) of a cell size of 0.1 µm2 and other critical features across the chip with a process window are demonstrated.

Paper Details

Date Published: 1 January 2010
PDF: 4 pages
J. Micro/Nanolith. MEMS MOEMS 9(1) 013001 doi: 10.1117/1.3302125
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 9, Issue 1
Show Author Affiliations
Ryoung-Han Kim, GLOBALFOUNDRIES Inc. (United States)
Steven J. Holmes, IBM Thomas J. Watson Research Ctr. (United States)
Scott D. Halle, IBM Corp. (United States)
Vito Dai, GLOBALFOUNDRIES Inc. (United States)
Jason E. Meiring, IBM Corp. (United States)
Aasutosh D. Dave, Mentor Graphics Corp. (United States)
Matthew E. Colburn, IBM Corp. (United States)
Harry J. Levinson, GLOBALFOUNDRIES Inc. (United States)

© SPIE. Terms of Use
Back to Top