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Journal of Micro/Nanolithography, MEMS, and MOEMS

Design-specific variation in pattern transfer by via/contact etch process: full-chip analysis
Author(s): Valeriy Sukharev; Ara Markosian; Armen Kteyan; Levon Manukyan; Nikolay Khachatryan; Jun-Ho Choy; Hasmik Lazaryan; Henrik Hovsepyan; Seiji Onoue; Takuo Kikuchi; Tetsuya Kamigaki
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Paper Abstract

A novel model-based algorithm provides a capability to control full-chip design-specific variation in pattern transfer caused by via/contact etch (VCE) processes. This physics-based algorithm is capable of detecting and reporting etch hot spots based on the fabrication-defined thresholds of acceptable variations in critical dimension (CD) of etched shapes. It can be used also as a tool for etch process optimization to capture the impact of a variety of patterns presented in a particular design. A realistic set of process parameters employed by the developed model allows using this novel VCE electronic design automation tool for design-aware process optimization in addition to the "standard" process-aware design optimization.

Paper Details

Date Published: 1 October 2009
PDF: 12 pages
J. Micro/Nanolith. 8(4) 043007 doi: 10.1117/1.3268422
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 8, Issue 4
Show Author Affiliations
Valeriy Sukharev, Mentor Graphics Corp. (United States)
Ara Markosian, Mentor Graphics Corp. (United States)
Armen Kteyan, Mentor Graphics Corp. (Armenia)
Levon Manukyan, Mentor Graphics Corp. (Armenia)
Nikolay Khachatryan, Mentor Graphics Corp. (Armenia)
Jun-Ho Choy, Mentor Graphics Corp. (United States)
Hasmik Lazaryan, Mentor Graphics Corp. (Armenia)
Henrik Hovsepyan, Mentor Graphics Corp. (Armenia)
Seiji Onoue, Toshiba Corp. (Japan)
Takuo Kikuchi, Toshiba Corp. (Japan)
Tetsuya Kamigaki, Toshiba Microelectronics Corp. (Japan)

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