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Journal of Electronic Imaging

High-performance very large scale integration architecture design for various-ratio image scaling
Author(s): Chung C. Lin; Ming-hwa Sheu; Huann-keng Chiang; Chishyan Liaw
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Paper Abstract

This paper presents a low-cost and high-speed architecture of bicubic convolution interpolation for high-quality digital image scaling. This architecture reduces the computational complexity of generating weighting coefficients and number of memory access times. Furthermore, it attempts to minimize the error propagation that results from the fraction truncations when calculating pixel coordinates under fixed-point operations. Error propagation significantly diminishes the output image quality for hardware interpolation. In order to avoid the inaccuracy accumulation, a simple periodical compensation technique is presented to improve the average root-mean-square error significantly. From the perspective of hardware cost, the presented architecture has ~50% saving compared to the latest bi-cubic hardware design work. Finally, this architecture has been successfully designed and implemented with Taiwan Semiconductor Manufacturing Company (TSMC) 0.13 µm complimentary metal oxide semiconductor technology. The simulation results demonstrate that the high-performance architecture of bicubic convolution interpolation at 279 MHz with 30643 gates in a 498×498 µm chip is able to process various-ratio image scaling for full high-definition display device in real time.

Paper Details

Date Published: 1 October 2008
PDF: 11 pages
J. Electron. Imaging. 17(4) 043010 doi: 10.1117/1.3010883
Published in: Journal of Electronic Imaging Volume 17, Issue 4
Show Author Affiliations
Chung C. Lin, National Yunlin Univ. of Science and Technology (Taiwan)
Ming-hwa Sheu, National Yunlin Univ. of Science and Technology (Taiwan)
Huann-keng Chiang, National Yunlin Univ. of Science and Technology (Taiwan)
Chishyan Liaw, Tunghai Univ. (Taiwan)


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