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Journal of Micro/Nanolithography, MEMS, and MOEMS

Automated hot-spot fixing system applied to the metal layers of 65-nm logic devices
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Paper Abstract

Hot-spot clearance using process simulation is indispensable for low-k1 lithography processes. Hot spots will occur mainly depending on local pattern context. Appropriate calibration of design rules, mask data preparation, resolution enhancement techniques, and optical proximity effect correction will reduce potential hot spots. However, pattern layout variety is so enormous that, even with the most careful calibration of every process, an unexpected potential hot spot is occasionally left in the design layout. Manual modification of the design at the hot spot will be effective, but it takes too much time. Therefore, there is a need for an automated hot-spot fixing system so as to avoid fatal hot-spot occurrence, with sufficient process margins and short turnaround time. We developed an automated hot-spot fixing system, the hot-spot fixer (HSF). Design data is automatically modified according to the instruction at every hot spot, complying with the design rule. We applied the HSF system to the metal layer of logic devices of 65 nm and most of the hot spots were diminished throughout a full chip within 12 hours. Thus, HSF feasibility has been proved for metal layers in the 65-nm node and below with full-chip data volume.

Paper Details

Date Published: 1 July 2007
PDF: 6 pages
J. Micro/Nanolith. 6(3) 031010 doi: 10.1117/1.2785030
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 6, Issue 3
Show Author Affiliations
Sachiko Kobayashi, Toshiba Corp. (Japan)
Suigen Kyoh, Toshiba Corp. (Japan)
Toshiya Kotani, Toshiba Corp. (Japan)
Satoshi Tanaka, Toshiba Corp. (Japan)
Soichi Inoue, Toshiba Corp. (Japan)

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