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Journal of Micro/Nanolithography, MEMS, and MOEMS

Lithography-simulation-based design for manufacturability rule development: an integrated circuit design house's approach
Author(s): Jonathan Ho; Yan Wang; Joanne Wu; Ya-Ching Hou; Ke-Chih Wu
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Paper Abstract

We describe design house approaches for design rule developments with emphasis of valuations of pre-optical proximity correction (pre-OPC) layouts and their simulation results. To begin, we describe the procedure of the simulation model calibration. An evaluation of metrics for analyzing the design layouts is then described. Due to the unavailability of post-OPC layouts, both pre-OPC and trial-OPC simulations are studied. A range of layout pattern density, within which the pre-OPC metric follows the post-OPC's, is estimated. Within this pattern density range, pre-OPC layout then can be evaluated to identify potential process "hot spots." With this approach, a set of design for manufacturability (DFM) compliance design rules is derived and applied to the product developments for both 90- and 65-nm process technology nodes. Several hot spots in the products (designed with 90-nm design rules) are located and fixed using layout optimization guided by the DFM rules. Simulated image contours and in-line scanning electron microscope (SEM) images validate the approach.

Paper Details

Date Published: 1 July 2007
PDF: 10 pages
J. Micro/Nanolith. MEMS MOEMS 6(3) 031008 doi: 10.1117/1.2781584
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 6, Issue 3
Show Author Affiliations
Jonathan Ho, Xilinx, Inc. (United States)
Yan Wang, Xilinx, Inc. (United States)
Joanne Wu, Anchor Semiconductor Inc. (United States)
Ya-Ching Hou, United Microelectronics Corp. (Taiwan)
Ke-Chih Wu, Anchor Semiconductor Inc. (United States)

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