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Journal of Micro/Nanolithography, MEMS, and MOEMS

Layout techniques and rules to reduce process-related variability
Author(s): Artur P. Balasinski; Joseph Cetin; Linard N. Karklin
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Paper Abstract

Variability of electrical parameters across the product die and wafer compromises functionality and yield of integrated device families in the sub-100-nm technologies, such as System-on-Chip. We discuss variability reduction through: Tightening manufacturing process variability, design-for-manufacturability (DFM) rules, and parameterized, correct-by-construction (CBC) layout. While so far the best option for variability reduction has been to improve process capability without impacting product design, it may no longer be preferred due to continuously increasing processes cost driven by technology shrinks. Currently, the CBC parametric layout emerges as the best option, with parametric variability traded for device footprint or the aggressiveness of the resolution enhancement techniques [e.g., optical proximity correction (OPC)]. The least favorable from the product flow standpoint is the layout-time addition of design rules or OPC in response to the localized issues in a random layout (hot spots), which causes reworks and delays, or compromises the process window. For the optimal parameterized layout, we discuss rule development for MOSFET gate length variation and dummy device placement. In summary, a number of tradeoffs are necessary for the design optimization to minimize device variability, depending on the product application.

Paper Details

Date Published: 1 July 2007
PDF: 8 pages
J. Micro/Nanolith. 6(3) 031009 doi: 10.1117/1.2775471
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 6, Issue 3
Show Author Affiliations
Artur P. Balasinski, Cypress Semiconductor Corp. (United States)
Joseph Cetin, Cypress Semiconductor Corp. (United States)
Linard N. Karklin, Sagantec North America (United States)

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