Optical EngineeringApplication based on dynamic reconfiguration of field-programmable gate arrays: JPEG 2000 arithmetic decoder
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This paper describes the implementation of a part of the JPEG 2000 algorithm (MQ decoder and arithmetic decoder) on a field-programmable gate array (FPGA) board by using dynamic reconfiguration. A comparison between static and dynamic reconfiguration is presented, and new analysis criteria (spatiotemporal efficiency, logic cost, and performance time) have been defined. The MQ decoder and arithmetic decoder are attractive for dynamic reconfiguration implementation in applications without parallel processing. This implementation is done on an architecture designed to study the dynamic reconfiguration of FPGAs: the ARDOISE architecture. The obtained implementation, based on four partial configurations of the arithmetic decoder, allows one to reduce the number of logic cells significantly (by 57%) in comparison with static implementation.