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Optical Engineering

622-Mbit/s burst-mode clock and data recovery circuit with duty control in a jitter reduction circuit
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Paper Abstract

A clock and data recovery circuit using the clock jitter reduction technique is proposed for a 622-Mbit/s burst-mode data stream. The clock jitter reduction is achieved by controlling the clock duty cycle with the phase information of the recovered clock. The proposed clock recovery circuit, based on the gated oscillator, recovers a low-jitter output clock with up to 4090 consecutive zeros.

Paper Details

Date Published: 1 August 2005
PDF: 4 pages
Opt. Eng. 44(8) 085004 doi: 10.1117/1.2012328
Published in: Optical Engineering Volume 44, Issue 8
Show Author Affiliations
Chul-Soo Park, Gwangju Institute of Science and Technology (South Korea)
Chung-Ghiu Lee, Korea Photonics Technology Institute (South Korea)
Chang-Soo Park, Gwangju Institute of Science and Technology (South Korea)


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