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Journal of Micro/Nanolithography, MEMS, and MOEMS

Simulation studies and experimental verification of the performance of a lithocell combination bake-chill station
Author(s): Arunn Narasimhan; Natarajan Ram Ramanan
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Paper Abstract

Simulation studies along with the necessary experimental verification of the performance of a new combination bake-chill station designed by FSI International in its POLARIS® thermal road-map project is presented in this paper. Since in this new design the 300-mm wafer is heated to the desired bake temperature and chilled back to room temperature before removed out of the station, a tight temperature control of the wafer throughout the process is achieved. To analyze the thermal performance of the station, an axi-symmetric model and a three-dimensional model geometrically similar to the new station are generated. The commercial CFD software Fluent® is employed to solve the Navier Stokes and energy equations in the computational domain. Experimental data as measured by a 42-point OnWaferTM temperature sensor wafer is used to verify the predictions of the simulated transient temperature behavior from the numerical model on the new station. Further, the simulations and experiments presented here substantiate the thermal agility of the proposed combination bake-chill station design. Higher throughput of the cluster, a major productivity improvement contribution of this new design, is also presented. Influence of the combination bake-chill station mechanical and thermal design losses on the wafer surface temperature uniformity and suggestions for improvements are also discussed.

Paper Details

Date Published: 1 April 2004
PDF: 7 pages
J. Micro/Nanolith. 3(2) doi: 10.1117/1.1668269
Published in: Journal of Micro/Nanolithography, MEMS, and MOEMS Volume 3, Issue 2
Show Author Affiliations
Arunn Narasimhan, FSI International, Inc. (United States)
Natarajan Ram Ramanan, FSI International, Inc. (United States)


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