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Journal of Electronic Imaging

Real-time field programmable gate array architecture for computer vision
Author(s): Miguel Arias-Estrada; Cesar Torres-Huitzil
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Paper Abstract

This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low-level image processing. The field programmable gate array (FPGA)-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and it is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but it can be implemented on dedicated very-large-scale-integrated devices to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real-time performance are discussed. Some results are presented and discussed.

Paper Details

Date Published: 1 January 2001
PDF: 8 pages
J. Electron. Imag. 10(1) doi: 10.1117/1.1329341
Published in: Journal of Electronic Imaging Volume 10, Issue 1
Show Author Affiliations
Miguel Arias-Estrada, Instituto Nacional de Astrofisica Optica y Electronica (Mexico)
Cesar Torres-Huitzil, Instituto Nacional de Astrofisica, Optica y Electronica (Mexico)

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