San Jose Marriott and San Jose Convention Center
San Jose, California, United States
26 February - 2 March 2017
Plenary Events
Welcome and Announcements
Date: Monday 27 February 2017
Time: 8:00 AM - 8:30 AM
Location: Convention Center 220A
Symposium Chairs: Bruce W. Smith, Rochester Institute of Technology (USA) and Will Conley, Cymer, An ASML company (USA)

Introduction of New SPIE Fellows

Award Presentations

14th Frits Zernike Award for Advances in Optical Microlithography

Plenary Presentations
Date: Monday 27 February 2017
Time: 8:30 AM - 10:30 AM
Location: Convention Center 220A
Plenary Presentations Sponsored by

8:30 to 9:10 AM

Photomask Challenges for Upcoming Technology Nodes

Frank E. Abboud
Vice President, Technology and Manufacturing Group
General Manager, Intel Mask Operation (USA)

Nearly all microchips used today are manufactured using projection lithography. Although other techniques are available, projection lithography has become the industry standard because of its applicability to mass production. At the core of lithography is the photomask, containing a physical image of each microchip layer. Since the advent of microchips the integrated circuit density continues to increase at a rate predicted by Moore’s law (Moore 1965). Such a dramatic increase is primarily possible due to the reduction in the critical dimension of the main transistor structure. In the past ten years this reduction has reached an impressive level where the scanners’ wavelength reached a plateau at 193nm while the minimum feature size continued to shrink to today’s production wafers of about 14nm, with plans for as low as 5nm. The ability to pattern features almost 20 times smaller than the size of the imaging light source wavelength was only made possible by using Resolution Enhancement Techniques (RET), Optical Proximity Correction (OPC) and Phase Shift Mask (PSM), building on photomask technology. Going into the 13.5nm wavelength era, the photomask continues to take center stage. Advancements in photomask materials, tooling, patterning and manufacturing techniques have enabled the early exposure of EUV wafers and have paved the way for eventual integration into wafer fabs. This paper will give a historical perspective of the advancements and achievements of photomask manufacturing that are fueling the microchip industry and the key challenges and focus areas to keep the photomask industry relevant for upcoming technology nodes.

9:10 to 9:50 AM

Inspection and Metrology to Support the Quest for Perfection: Photolithography for the Sub-10nm Nodes

Ben (Bin-Ming) Tsai
Chief Technology Officer and Executive Vice President of Corporate Alliances
KLA-Tencor Corp. (USA)

In order to successfully realize the sub-10nm lithography roadmap, photolithographers and equipment and materials suppliers must work in close collaboration to mitigate yield-limiting defects and process variations in order to raise device yields and ensure robust progress in innovation. For more than 40 years, inspection and metrology equipment suppliers have led the semiconductor industry with innovative breakthroughs in process control; developing inspection and metrology solutions that address key lithography challenges. This presentation will outline the process control challenges that lay ahead, highlight examples of technology innovations and those that are under development that will support the ecosystem of innovation and collaboration to help realize the sub-10nm lithography roadmap.

9:50 to 10:30 AM

Materials Innovation: It’s No Longer Only About Resolution

Nobu Koshiba
President and CEO
JSR Corp. (USA)

The entire electronic materials market is continually pushed node over node. In the past, the progression of exposure wavelengths that enabled advancement against Moore’s law gave rise to new resist chemistries that would then undergo years of refinement and optimization to squeeze the maximum resolution and CD control from each platform. The push on materials for resolution and process latitude continues today, but these are becoming secondary to new focus areas such as the material contributions to edge placement error (LWR, CDU), planarization, gap filling, and etch selectivity. At the same time these new materials must be introduced with lower and lower defect contributions. Originally, many materials suppliers focused mainly on supporting their customers with photoresist solutions within the electronic materials space. Today suppliers continue to develop new photoresists, but have expanded into complementary segments such as organic underlayers, spin-on metal antireflective coatings, topcoats, a variety of shrinking and slimming approaches as well as CMP pads & slurries. Semiconductor integration of new materials from across the periodic table leads us to develop new wet-cleaning chemistries, and even materials that self-assemble in bottom’s up patterning. In parallel segments such as 2.5D and 3D packaging bring on new challenges in the space of advancing thick resists for plating applications and permanent spin on dielectrics. Additionally, advances in display technology needs, along with CMOS image sensors bring even further challenges to the materials suppliers. As our view within electronic materials expands, we have a unique perspective into how materials are influencing and shaping the electronic industry. This talk will present an overview with the long term vision of our future digital society including how electronics industry evolves and how materials fits into the larger picture.

Coffee Break 10:30 to 11:00 AM
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