San Jose Convention Center
San Jose, California, United States
25 February - 1 March 2018
Plenary Events
Welcome and Announcements
Date: Monday 26 February 2018
Time: 8:00 AM - 10:30 AM
Location: Convention Center, 220A
Welcome and Announcements
8:00 am to 8:30 am

Symposium Chairs: Bruce W. Smith, Rochester Institute of Technology (USA) and Will Conley, Cymer-An ASML company (USA)

Introduction of New SPIE Fellows

15th Frits Zernike Award for Advances in Optical Microlithography

Plenary Presentations Sponsored by


8:30 to 9:10 AM

Moore's Law At and Beyond 5nm

Yan Borodovsky
SPIE Fellow, Intel Senior Fellow (Retired) (USA)

For over 50 years, the Semiconductor Industry ecosystem supported high volume manufacturing of ICs that followed the famous Gordon Moore’s exponential transistors density and cost rate of change prediction. Yet resolution and “raw” EPE control of Lithography Exposure tools used in High Volume Manufacturing were and are lagging IC patterning needs as demanded by the economy of Moore’s Law for last 20+ years. As a result, the ever more complex patterning techniques that result in additional wafer cost were introduced at every node driving intra-node wafer cost growth from a traditional 10% to 30% or more. This in turn resulted in need for significant change in the approach to IC design layout rules definitions, higher capital equipment reuse rates, significant change in CAD and mask making equipment, and other important changes to wafer and mask making infrastructure. Due to the complex relations between patterning costs, device design rules, device architecture, various and different sets of imaging, the etching, thin films and CAD tools and materials needed to support various existing and expected to materialize routes of wafers processing IC manufacturers face difficult choices. This is true in regards to managing the R&D resource allocation capable to identify optimal strategy for 5nm node and beyond that will continue the historical trend of IC inter-node rate of area density growth and cost per transistor reduction. All of this while keeping inter-node cadence within historical 2-3 year timeframe. With the advent of new for HVM patterning approaches such as EUV, DSA, and selective deposition, the level and impact of stochastically introduced defects on process yields, if not contained, may rise dramatically with detrimental impact to future nodes development cycles and wafer costs. Correspondingly resurrection of old design methods (redundancy), expansion of existing ones (Built-In-Self-Test) as well as development and introduction of new methods and tools, specifically targeting understanding and mitigation of such defects during development as well as HVM needs to be deployed starting now and employed in the not so distant future. Introduction of such new to HVM patterning techniques and maturation of processes build on its basis during the next technology nodes starting with 5nm will see progressively larger portion of computing content on the chip moving from von-Neumann architecture to different ones such as neural nets and neuromorphic computing that might or will exhibit significantly different yield sensitivities from von-Neumann portion of the chip. Understanding such differentiated sensitivities to stochastically introduced defects in advance needs to be developed in order to properly design process development test chip and defects testing methodology as well as corresponding HVM wafers disposition approach.

Yan Borodovsky came to U.S. at the age of 32 from Kiev, Ukraine in 1979 where he lived and worked in Institute of Nuclear Research of Academy of Science from age of 18 developing ultra-pure semiconductor materials and devices for nuclear radiation spectrometry. In parallel with working Yan got his MS in Solid State devices from Tula Polytechnic in 1971. Upon coming to US/California Yan worked at Syncal Corporation during 1979-1982 developing semiconductor thermoelectric conversion materials for deep space satellites power supplies. He started his carrier as a lithographer at AMD in 1982 and in 1985 moved to Oregon to join start-up ATEQ where he worked developing optical path design and assembly, optics test stand and resist process for CORE 2000 laser writer (known as Alta mask laser writer after ATEQ sale to ETEC/Applied Materials). Yan joined Intel as Staff Litho Engineer in 1987. During following 28 years at Intel Yan worked on all aspects of Intel Lithography and led Intel Lithography Roadmap development, numerous novel lithography processes, tools and materials Pathfinding and Development as well as process-design co-optimization efforts to enable Intel leadership position for multiple technology nodes starting with 0.5micron and ending at 7nm Technology Node at the time of his retirement in July of 2015. Yan is author of many US patents, publications and multiple presentations at key Lithography Forums. Yan contributions to Intel were recognized by appointing Yan to ranks of Intel Fellows in 1999 and to newly established position of Intel Sr. Fellow in 2003. His contribution to Microlithography were recognized by SPIE electing Yan to position of SPIE Fellow in 2013 and to Industry contribution overall by awarding him annual IEEE Cledo Brunetti Award in 2012 “For contributions to developing and implementing innovative lithographic and patterning equipment and processes to enable cost-effective scaling for logic technologies.” In 2016 SPIE awarded Yan prestigious annual Frits Zernike Award “in recognition of his efforts toward the advancement of multi-generational lithography process solutions and as a key contributor of patterning approaches and layout design rules at Intel”.

9:10 to 9:50 AM

Moore's Law, Lithography, and How Optics Drive the Semiconductor Industry

G. Dan Hutcheson
CEO and Chairman
VLSI Research Inc. (USA)

When the subject of Moore's Law arises, the important role that lithography plays and how advances in optics have made it all possible is seldom brought up the world outside of lithography itself. When lithography is mentioned up in the value chain, it’s often a critique of how the advances are coming too slow and are getting far too expensive. Yet advances in lithography are at the core of how Moore’s Law is viable. This presentation lays out how technology and the economics of optics in manufacturing interleave to drive the immense value that semiconductors have brought to the world by making it smarter. Continuing these advances will be critical as electronics make the move from smart to cognitive. So how is it possible that the history of lithography is one where the price of a single tool has soared from 10 cents to today's $100M+ EUV behemoths and yet the business still thrives? There are fundamental economic engines underlying this that make the rising cost of lithography affordable given that there are technical advances in optics.

Dan Hutcheson is CEO and Chairman of VLSIresearch Inc. He is a recognized authority on the semiconductor industry, winning SEMI’s Sales and Marketing Excellence Award in 2012 for “empowering executives with tremendous strategic and tactical marketing value” through his e-letter, The Chip Insider®; his book Maxims of Hi-Tech, and his many interviews of executives. He is thought of as “the marketing voice and expert for the industry.” Dan has methodically captured the essence of the industry and produced it in such a way for all to benefit. He has been such an integral part of the industry for so long, it is difficult to imagine the industry without his contributions. His consulting work has included hundreds of successful programs involving product development, launch, and positioning. Dan has a proven track record of developing economic models that accurately predict trends. He is widely known for the forecasting of strategic infrastructure shifts. This includes his early-eighties development of the first factory cost-of-ownership models, multiple wafer size and lithography transitions, the rise of the fabless/foundry model to counter escalating fab costs, the shift of the DRAM memory market from the United States to Japan in the 1980s, then its shifting again to Korea in 1990s, as well as the driving forces behind the rise of Flash Memory. Dan’s public work on the industry includes two articles for Scientific American challenging predictions of the demise of Moore’s Law by demonstrating how the innate abilities of scientists to innovate have outpaced the doomsayers, and an invited article on the history and economics of Moore’s Law for the SIA. He has also been the keynote or invited speaker at dozens of conferences. His pro bono work has included serving as an advisor on innovation to the White House Council of Economic Advisors, teaching invited courses at Stanford University, and serving on the Board of Advisors to the Extension School at UC Berkeley. Dan holds two patents and a Master’s degree in Economics from San Jose State University. He is a senior member of the IEEE.

9:50 to 10:30 AM

The Challenges of Resolution Enhancement Techniques for Advanced Technology Development

Stephen Hsu
Fellow, ASML Brion (USA)

The idea of “optimum mask and source patterns to print a given shape” was introduced in 2001 as a resolution enhancement technique (RET). Socha optimized the source and mask by maximizing the worst image log slope (ILS) through a depth of focus (DOF) range. To achieve a robust Source/Mask Optimization (SMO) solution, the optimization flow and cost function are important parts of the SMO design. The use of an intuitive cost function based on Edge Placement Error (EPE), can provide maximum flexibility for co-optimizing the source and mask. Minimizing EPE for a set of evaluation points on the design target across different process window (PW) conditions results in an approach that is directly linked to critical dimension (CD), pattern placement error and image log slope (ILS), and offers insight into the root causes of variability for the critical layers of advanced logic and memory devices.

One unique advantage that was developed within the Source/Mask Optimization was the ability to place sub-resolution assist features (SRAFs) based on an inverse Continuous Transmission Mask (CTM) map to enhance imaging performance across features. The CTM is a pixel-based gray-scale inverse mask which allows freeform source mask and SRAF co-optimization to produce the best imaging performance. This is a very powerful capability for optimizing the imaging of advanced logic devices. Inverse Lithography Technology (ILT) was explored by B.E.A. Saleh and later by Luminescent to find the optimal mask by applying a rigorous mathematical solution. Although these early ILT approaches often resulted in superb lithography, they were generally impractical in a production environment. Run times were many orders of magnitude longer than model based OPC, and the resulting masks were often too complex to manufacture. The introduction of the multi-beam mask writers enables ILT to become a practical solution. CTM map optimization is very computationally expensive and cannot be scaled to full chip. With the rise of big data, the improvement in the high performance computing and the advancement in machine learning, techniques involving Deep Convolutional Neural Networks (DCNNs) can be used to “learn the optimal SRAF placement” from CTM maps and apply that learning to full chip. Since SRAF training is done prior to full chip OPC, machine learning assisted SRAF placement can achieve superior process window performance, and significantly reduce run time compared to inverse lithography based SRAF placement.

As SMO has continued to improve to meet the imaging challenges for advanced technology nodes, its capabilities have been significantly expanded beyond just source and mask optimization. All four “imaging planes” can be optimized: source, mask, wavefront, and design target. This co-optimization approach bridges the gap between process optimization for the scanner and target design optimization for manufacturing.

With remarkable progress in improving EUV source power, photoresist, and pellicles, chip makers are actively working on the adoption of 0.33 numerical aperture (NA) EUV scanners for high volume manufacturing. SMO has continued to evolve to address the new challenges of EUV: small wavelength to reticle stack ratio causing strong mask topology effects, absorber shadowing effects, and stochastic effects. The greatest challenge in EUV SMO is balancing the traditional imaging metrics of process window, mask error factor, and process variation (PV) band with the EUV-related concerns of pattern placement error (PPE) and stochastic effects. For EUV lithography, SMO provides the capability of balancing all of the above imaging metrics of interest to achieve the desired results.

Currently, leading foundries and integrated device manufacturers are starting to investigate patterning options beyond the 5nm node. To minimize the cost and process complexity of multiple patterning beyond the 5nm node, EUV high-NA single exposure patterning is preferred over EUV double patterning. As EUV high-NA scanners are equipped with a 0.55 NA anamorphic projection optics with center obscuration, EUV high-NA SMO needs to include the anamorphic nature of the system in its models, including the center obscuration effect and anamorphic mask manufacturing rule check (MRC), during mask optimization.

SMO has become an advanced technology development platform, widely used by all leading logic and memory chip makers, not only to define the optimal illumination source shape, but also to explore designs and perform pathfinding for different patterning solutions and to guide the direction of future designs and enable the scaling roadmap.

Stephen D. Hsu is an ASML Fellow and the product lead of imaging product engineering at ASML Brion. Stephen started to work in the field of lithography at Xerox Microelectronics Center as a GCA 5X g-line stepper engineer and later joined National Semiconductor Corporation, Fairchild research center as a staff process engineer where he worked on the i-line, KrF steppers and the first generation step and scan scanner PAS 5500/500. He worked at KLA Rapid Division prior to joining ASML in 2000 started to work on resolution enhancement techniques and computational lithography.

During the course of his career, Stephen has been working on all aspects of advanced lithography development over the past 27 years including: overlay/alignment optimization/control strategy, stepper/scanner characterization, reticle inspection, SMORET product development. In the past 17 years, he has been working on developing resolution enhancement technique (RET) solutions including: sub-resolution assist features (SRAF), Optical Proximity Correction (OPC), and DUV/EUV Source mask optimization (SMO) and has worked with customers worldwide to implement these in Foundries and IDM’s as practical low patterning solutions.

Presently he is focused on sub-7 nm patterning technology development, including the use of source mask optimization for ArF multiple patterning and EUV lithography. The development of Scanner proximity monitoring methodology, computational lens heating control products. Stephen has been regularly invited by SPIE to teach the “Principles and Practical Implementation of Multiple Patterning” short course at the Advanced Lithography Symposium for the past 11 years. He taught the “Principle and Practical implementation of Microlithography and Resolution enhancement techniques (RET)” internal short course at multiple sites in ASML.

He has authored 98 papers in lithography and resolution enhancement techniques and holds 39 patents related to advanced lithography and resolution enhancement techniques. Stephen’s patents and publications have received a total of 1194 citations.

Coffee Break 10:30 to 11:00 AM
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