San Jose Convention Center
San Jose, California, United States
24 - 28 February 2019
Plenary Events
Welcome and Plenary Presentations
Date: Monday 25 February 2019
Time: 8:00 AM - 10:30 AM
Location: Convention Center, Grand Ballroom 220A
8:00 am to 8:30 am
Welcome and Announcements

Symposium Chairs: Will Conley, Cymer-An ASML Company (United States) and Kafai Lai, IBM T. J. Watson Research Ctr. (United States)

Introduction of New SPIE Fellows

Presentation of the Zernike Awards

Presentation of the Nick Cobb Memorial Scholarship

8:30 am to 10:30 am
Plenary Presentations

8:30 am to 9:10 am
The Future is Quantum

Dario Gil, Chief Operating Officer
IBM Research (United States)

Some of the most important technical advances of the 20th century were enabled by decades of fundamental scientific exploration, whose initial purpose was simply to extend human understanding. This era marked the creation and widespread usage of “classical” computers, which represent information as bits – 0 and 1. Despite the continued computational advances we have experienced over the past century, there are still many important and relevant problems that “classical” computers cannot solve.
We are witnessing rapid progress in a new computing paradigm – Quantum Computing. Quantum computing takes advantage of the laws of quantum mechanics found in nature and represents a fundamental change from classical information processing. Two properties of quantum behavior – superposition and entanglement – may allow quantum computers to one day address problems intractable for today’s conventional classical machines.
During this talk, I will give an overview of quantum computing, what it means for the future of technology, and how we can separate hype from reality.

Dario Gil is the Chief Operating Officer of IBM Research, a global organization with over 3,000 researchers across 13 laboratories and 21 locations devoted to advancing the frontiers of information technology. As COO, Dr. Gil is responsible for guiding the strategic agenda of IBM Research, defining IBM’s annual Global Technology Outlook, driving operations and financial plan execution, and establishing partnerships with companies and universities worldwide. As the Vice President of AI and Quantum Computing, Dr. Gil is also responsible for IBM’s global research efforts in artificial intelligence and for IBM's quantum computing program. He co-chairs the MIT-IBM Watson AI Lab along with Professor Anantha Chandrakasan, Dean of the MIT School of Engineering. Dr. Gil’s research results have appeared in over 20 international journals and conferences and he is the author of numerous patents. Dr. Gil is an elected member of the IBM Academy of Technology. He received his Ph.D. in Electrical Engineering and Computer Science from MIT.

9:10 am to 9:50 am
3D NAND Flash Technology: Roadmap, Process, Design and Challenges

Jeongdong Choe, Senior Technical Fellow
TechInsights (Canada)

Due to many of technical barriers and issues on manufacturing 2D NAND Flash devices such as quadruple patterning technology (QPT), air-gap process, crosstalk/interference and CG/FG leaning, 3D NAND Flash architectures represent an opportunity to overcome the limitations of planar technology. Now, 3D NAND Flash technology is popular in industry and commercial market, and it is one of the most prominent integrated solution for the nonvolatile storage devices including SSD and high volumes of data. After Samsung mass-produced their modified TCAT 3D V-NAND with 24L in 2013, Toshiba/Western Digital BiCS, SK Hynix P-BiCS and Micron/Intel 3D FG CuA have been commercialized. Already, all the major NAND players reached up to 64L/72L and even more than 90L. Although NAND players are now free from QPT, 3D NAND technology challenges for further scaling down on 3D NAND process integration such as very high aspect ratio channel and source contact formation, charge leakage from trap layer, forming staircase/word line pad connection and multi-stack cell architecture are still on the list of their technology barriers. Different cell layouts/design, masks, patterning (Photolithography and Etching), process integration/sequence and materials have been used for each 3D NAND architecture. The general scaling trend for every 3D NAND Flash technology is to increase the number of integrated layers. How to successfully reach out the process integration for the next 3D NAND generation? We’ll review recent progress on 3D NAND cell architecture from major 3D NAND players. Future challenges/direction and prospection will be discussed as well.

Jeongdong Choe has a Ph.D. in electronic engineering and 26+ years’ experience in semiconductor process integration for DRAM, (V) NAND, SRAM and logic devices. Dr. Choe’s background includes positions as a Team Lead in R&D for SK-Hynix and Samsung, where he optimized process and device architectures with state-of-the-art technologies for mass production. He received a Ph. D., Electronics (Semiconductor) at Sungkyunkwan Univ.; a Master Degree, Materials Engineering (Metallurgical) at Yonsei Univ.; a Bachelor’s Degree, Metallurgical Engineering at Yonsei Univ.

9:50 am to 10:30 am
Patterning in the Stressful World of 3D NAND

Steven Steen Director, Product Management-3D Memory Software
ASML (Netherlands)

Bart van Schravendijk Chief Technology Officer, Dielectrics
Lam Research Corp. (United States)

Micheal Kubis Senior Management System Engineer
ASML (Netherlands)

Jan Willem Cromwijk Product System Engineer
ASML (Netherlands)

Hans Kattouw System Engineer for 3D NAND Device and Applications
ASML (Netherlands)

Yongsik Yu Managing Technical Director of Memory Program
Lam Research Corp. (United States)

3D NAND has become the mainstream technology powering NAND Flash to ever higher density. In 2D NAND scaling the lateral dimensions have reached fundamental physical and economic limits. Shrinking gate lengths limited the number of electrons available for storage, which degrades reliability. Shrinking spacings created coupling problems in one direction and did not leave enough room for the Inter Poly Dielectric in the other. The vertical (“3D”) stacking of NAND devices enables the gate lengths and spacings to be larger than in 2D NAND while increasing area efficiency, thereby eliminating the problems noted above. In addition, 3D NAND reduces lithographic requirements by relaxing the lateral dimensions.
The transition to the 3D NAND device drives greater process and integration complexity than any HVM device in the past. Node transitions now focus on increasing the device layer count as opposed to lateral scaling which brings a new set of challenges. In this presentation we will briefly review the build sequence and then discuss four critical areas affected by the move to 3 dimensions.
The heart of the 3D NAND device starts by making the mold stack for the gate and insulation layers. Extremely uniform layers are required to enable the subsequent patterning, as well as for control the gate dimensions. The pillar then inserted through all of these gate and insulation layers is where the vertical series of charge trap or floating gate transistors are formed that store the memory states. The process to make this memory hole is the key challenge for both etch and lithography given its importance to memory characteristics and the extremely high aspect ratio of the feature. We will discuss the need for co-optimization across the patterning process to enable high yielding devices.
The contacts to every device layer are enabled using so called staircase patterning to make each layer individually addressable. To pattern the staircase, lithography uses large area block masks to define the first edge around the memory array. On etching down the selected bi-layer, resist trim of over 500nm moves the lateral edge to the next step in the staircase. This process is repeated several times as long as the resist height is sufficient. For efficiency this uses very thick resists with good sidewall angle control, sidewall angle uniformity and trim/etch behavior.
The introduction of multi-tier device stacks brings an additional challenge. By stacking two blocks of half the total stack height the challenges on the memory hole patterning can be reduced. However, the two memory hole patterning steps require highly accurate alignment in order to ensure that during the subsequent materials depositions the two strings of transistors are fully connected. We will discuss how process induced overlay errors in these layers require new approaches to control overall alignment performance.
During this whole process flow, film stress, is of key importance. Film stresses depend on materials and processes but are also integration and design dependent. Imperfect management of the film stresses during the build process leaves residual stress which manifests itself in local and global deformations of the substrate. In order to minimize the impact on device yields, stress reduction throughout the process is pursued in conjunction with advanced focus and overlay controls on the scanner.
The discussed 3D NAND patterning challenges show how process innovations change the semiconductor world - not upside down, but from horizontal to vertical. At same time, they also show that this dramatic change of chip architecture brings new sets of requirements to deposition, etch, and lithography that will keep not only wafers but also engineers at elevated stress levels.

Steven Steen is director of Product Management at ASML. In this role he is responsible for the 3D Memory product portfolio at ASML. He studied at the Hogeschool Enschede and started his career at IBM’s T.J. Watson Research Center during the final stages of his education.
Leading edge innovation is the consistent thread during his 20 years’ experience in semiconductor R&D (of which 15 in lithography). Steven joined IBM in 1997 to develop and commercialize full chip timing diagnostics through Picosecond Imaging Circuit Analysis. In 2001, Steven joined the microelectronics research line and started his career in lithography there. During a wide variety of roles he worked to realize numerous device technologies and business opportunities. He moved to the Netherlands and joined ASML in 2012 to lead the definition and development of innovations and unique product offerings to ASML’s customers. Holder of over 22 US Patents and 35 published research papers, Steven continues to think of new applications and the challenges of the future. Outside of work he is often found near the water for sailing, swimming or other forms of water sports.

Bart van Schravendijk is currently Chief Technical Officer, Dielectrics at Lam Research Corporation, Fremont, CA, USA. At Lam, he is focused on emerging technologies in the dielectric deposition area. In recent years these have found their application in VNAND, MRAM and Phase Change memories. He has 30+ years of experience in wafer fabrication equipment development, process technology and process integration. He has authored over 95 patents and numerous publications.

Michael Kubis holds a PhD in physics. He worked 5 years in material science research before joining Semiconductor Industry in 2001. He worked as Process Engineer and Senior Manager in Deep-Trench technology DRAM R&D and HVM until joining ASML in 2010 were he became System Engineer for on-product overlay applications. He is now Senior Manager of the System Engineering Patterning Team at ASML.

Jan Willem Cromwijk is Product System Engineer for 3D Memory Solutions in ASML. He studied Mechanical Engineering at University of Twente, and graduated in the department of Fluid Dynamics and Heat Transfer on Modelling of Cavitation and Two-phase flows.
After a year at Cambridge University, Department of Applied Mathematics and Theoretical Physics, he started at TNO, the Netherlands Organization for Applied Scientific Research. In 1997 he joined Philips, in several positions within Research and Development of Philips Innovations Services and Philips Lighting. In 2007 he joined ASML, as System Engineer for Immersion, NXE 3100, in the EUV Source program, and since 2016 in the 3D Memory Solutions program.

Hans Kattouw studied Applied Physics at the University of Twente in the department of Low Temperatures and Superconductivity. After working as an IT consultant, he joined ASML in 2000 where he has held several positions within Development & Engineering, Customer Service, Product Management and now System Engineering. He has worked on the development of immersion lithography, and has extensive knowledge on focus, overlay and 3D NAND process and device technology. In his free time, he plays electric guitar and climbs mountains.

Yongsik Yu is managing technical director of memory program in advanced technology department of Lam Research Corp. He earned a doctorate degree in materials science from Univ. of Maryland at College Park, a master’s degree in metallurgical science and engineering from Stevens Institute of Technology, and a bachelor’s degree in metallurgical engineering from Hanyang Univ.. Before joining Lam Research, he worked at various semiconductor companies such as Novellus Systems and SK Hynix Inc. And, he holds 30+ patents and has authored numerous technical papers.

Coffee Break 10:30 am to 11:00 am
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