Novel Patterning Technologies 2025

The demand for high-precision positioning for nanofabrication applications in macroscopic working areas is steadily increasing. Due to a new level of complexity in micro- and nanoelectronic manufacturing, the extreme requirements for high-precision nanopositioning over travel ranges up to several millimeters and their combination with highly efficient nanofabrication processes are necessary. This contribution focuses on a planar Nano Fabrication Machine 100 (NFM-100) with a working range up to Ø 100 mm and its integrated tip-based measuring system, which can be used as an Atomic Force Microscope (AFM) as well as for Field-Emission-Scanning-Probe-Lithography (FESPL). The combination of both systems offers the possibility to fabricate and analyse micro- and nanostructures with high resolution and precision down to single nanometre range over large area in one single configuration without tool/sensor change. Various experiments will be presented by combining these systems for large-area scanning, with a focus on the demonstration of macroscopic AFM scans up to 100 mm. This will be followed by comprehensive investigations of nanofabrication over macroscopic areas.

Scanning probe lithography (SPL) offers a variety of physical and chemical techniques for surface modification, enabling the fabrication of customized, functional nanoscale features. These methods provide unmatched resolution, repeatability, and operational simplicity compared to other lithographic techniques. This paper reviews recent advancements in SPL driven by electrical and thermal effects, highlighting how these approaches address the fabrication of functional nanostructures. These advancements pave the way for next-generation nanotechnological applications, including single-dopant atomic devices, memristors, metasurfaces, nanofluidic devices, and more.

Thermal scanning probe lithography (t-SPL), possible with the NanoFrazor from Heidelberg Instruments, makes it possible to create nanostructures with real-time inspection and correction, in grayscale as well as in high resolution. These capabilities, combined with accurate, markerless second layer alignment and automation features, provide a versatile and unique nanofabrication tool for advances in nanophotonics, nanobiosystems, nanoelectronics and emerging materials research. Recent breakthroughs in throughput and maximum lithography area include parallelization of t-SPL and smart handling of large designs in software implementation. Full parallel operation of the NanoFrazor was recently demonstrated to enable the simultaneous and independent patterning of a set of ten designs on the same surface. Combining laser direct sublimation with parallelized t-SPL makes it possible to fabricate complete devices within one patterning session.

Nanoimprint Lithography is a potential successor to EUV lithography, with potential resolution below the 8 nm limit of EUV. Ultrahigh-precision NIL templates are made by writing sub-nm precision patterns on Si(001) using H Depassivation Lithography (HDL), followed by selective growth via atomic layer deposition (ALD) of TiO2, which is then used as an etch mask for Reactive Ion Etching (RIE) to form a 2.5D Si template, replicating the STM pattern, which would be transferred to a quartz template for manufacturing. We show that sub-10 nm feature sizes and full-pitch gratings with feature radius of curvature down to 1.5 nm in the lateral dimension can be achievable.

We showcase two-photon grayscale lithography (2GL®) with in-situ alignment as the next step towards scalable fabrication of micro-optics. While the laser-based direct write technology is known to create true 3D structures with sub-micron resolution, the use of grayscale lithography (2GL®) enables high-speed of the fabrication with surface roughness below 5nm and shape accuracy down to below 200nm. We demonstrate user friendly 3D detection algorithms in our nanoPrintX software for automatic alignment towards a variety of topographies and material platforms with very high accuracy better than 100 nm. The versatility of our approach is shown via micro-optical elements aligned to fiber tips, wafers, photonic edge couplers, and photonic grating couplers for improved coupling losses and beam quality. In one example, we demonstrate the automatic fabrication of 480 on-chip optical coupling elements on a photonic integrated circuit with excellent optical surface qualities and highly reproducible placement accuracy.

In this presentation I will report our latest advances in 3-color lithography, which include simple and generalizable optical approaches for improving resolution by reducing flare, new approaches for achieving optimal alignment of the optical beams in our tool, and rational methods for designing 3-color photoresists with improved properties. These strategies have already led to substantial improvements in the resolution that we can achieve, and we expect to reach the 60-nm mark or better before the end of 2024.

Optical direct write technology has been expected for the applications of small volume production, chip-unique pattern writing, adjustable patterning, and large area printing for heterogeneous integration as the advanced packaging. There have been several schemes of the optical direct write systems, based on different levels of resolution and applications. Basic structure is common that one or multiple micromirror devices are used instead of the conventional mask of the exposure scanners. On the other hand, there are several key points that should be carefully designed for the direct write systems. In this paper, we present the progress of the optical direct write technology, referring the recent Digital Scanner development as an example, which is expected to have the same optical resolution as conventional 248nm, 193nm and immersion scanners, with throughput range from 0.5 wph to 20 wph.

3D nanoprinting using Two-Photon Polymerization (TPP) has advanced significantly, with applications expanding beyond scientific research to industrial uses. Despite TPP’s design flexibility and high structural quality, limited throughput remains a challenge due to its single-focus scan approach. Current methods to enhance throughput often increase process complexity. This paper addresses key factors influencing fabrication time: number of slices and exposure time per slice. By locally controlling voxel size, throughput can be increased up to 50-fold. High-speed scanning boosts hatch rates, increasing throughput by 5-fold. Combining these techniques raises throughput up to 250-fold, promoting broader industrial adoption of TPP.

The semiconductor industry must address the dual impact of digital technology with a comprehensive approach to overcome growth challenges while ensuring sustainability. This approach is crucial for balancing the environmental benefits and demands of rapid technological expansion. To support this, several collaborative programs funded by Horizon Europe are focusing on making semiconductor manufacturing more sustainable. These initiatives aim to align with the European Green Deal by implementing eco-friendly technologies and practices. By integrating innovations and adopting sustainable processes, the industry can reduce its environmental footprint and advance towards long-term sustainability. This holistic strategy will enable the semiconductor sector to meet its growth objectives while addressing increasing environmental constraints effectively.

Technology is playing an ever-greater role in enabling novel solutions for key challenges in the healthcare sector. From early discovery all the way to therapeutic intervention, creative technology solutions combined with improved biological understanding are driving a bioconvergence wave that can radically impact the future of healthcare. Underlying many of these advances are semiconductor chip technologies. For example, recent advances in artificial intelligence leverage enormous advances in compute power. But the basic silicon nanotechnology that underpins computational improvements can also enable the interrogation of biology at the most fundamental of length scales. In this presentation, I will share some of imec’s work in using chip technologies and advanced lithography to develop solutions for life science and medical device applications.

Some of the main bottlenecks preventing high data-rate systems are power consumption and data storage. In this talk, we will show our recent works on designing and fabricating analog photonic encoders that could address this challenge, enabling high-speed image compression and image processing using orders-of-magnitude lower power than digital electronics. Our approach relies on a silicon-photonics front-end to compress raw image data, foregoing energy-intensive image conditioning and reducing data storage requirements. Our opto-electronic data processing scheme has the potential to process data streams exceeding Terapixel/second using less than 100 fJ/pixel, providing a path to ultra-high-resolution data and image acquisition systems.

The fidelity of pattern transfer has increased in importance over time driven by critical interactions between mask pattern, wafer imaging and device performance. At the same time, increases in mask pattern complexity have complicated characterization while total edge placement error (EPE) takes center stage as a pattern transfer metric. We will consider aspects of image quality (IQ) in mask patterning with emphasis on complex 2D shapes such as those arising from broader use of curvilinear geometries. We will cover recent advancements that have allowed improvement in mask IQ including model driven mask treatment and high resolution multi beam mask writing. Methods to characterize, model and most importantly apply IQ in optimization for various applications will be reviewed. At the same time, we find metrology is becoming a gating step in understanding and further driving these improvements and provide perspective on how this part of the roadmap might evolve to serve photomask IQ objectives.

This paper publishes for the first time a full Online reticle curvilinear Mask Process Correction that includes linearity correction due to variable bias for production use in a mask shop. Micron is readying ourselves for EUV use of free-form curvilinear ILT by anticipating the need for full reticle processing of Mask Process Correction (MPC) including dose-based near-term and mid-range effects and variable bias for process effects that are not dose based. We have verified that such a capability works with inline processing as the machine writes the mask. The correction was verified on several full reticle curvilinear free-form patterns for EUV using 16nm pixel multibeam writer, the MBM-2000PLUS with the Pixel-Level Dose Correction (PLDC) capability. CD linearity down to 40nm mask features were shown to be within 1nm. As all corrections are performed inline, there is no separate preprocessing step that takes turnaround time (TAT), or explodes the file sizes due to mask process correction. This is a zero TAT solution where files output by ILT and verified by mask rules check (MRC) can be read directly by the mask writer for immediate processing.

We are developing the multi-beam mask writer MBM-4000, which will follow MBM-3000 that was released in 2023 and now deployed to customers’ sites for production of EUV-masks. The target technology node of MBM-4000 is A10 for which high-NA EUV is likely to be inserted. Therefore, in MBM-4000, we focus on patterning resolution improvement by applying the smaller beam size and the finer dose calculation mesh than MBM-3000. We also address improvements in CD uniformity and image placement accuracy by measures of hardware and software; the new writing strategy is applied, the resist thermal effect correction (TEC) is developed and the charge effect reduction (CER) is upgraded to version 3.0. Currently MBM-4000 is in its integration phase, and the writing performance test is already commenced to verify the tool design. In this paper, we will give an overview of MBM-4000 and discuss its performance with writing test results.

The versatility of MBMW multi-beam mask writers

In this market research study, we deep dive into Electron-Beam Writer equipment market from the perspective of the overall semiconductor ecosystem, i.e. equipment supply chain, applications where equipment is used, and relevant actors. We assess the 2023 electron-beam writer equipment (single- and multi-beam) market size at 1.25USDB, growing to 1.57USDB in 2029. This market size is only at 1% of the total wafer-processing equipment market but its evolution is critical for across all types of semiconductor devices. Consequently, we explore Electron-Beam Writer technology and related actors. We study upstream supply chains such as equipment subsystems and downstream equipment users, such as photomask shops for related technology and market aspects.

As scaling down advances, the maturity of EUV has improved, and the track record of its application to high-volume mass production has improved. On the other hand, the technology of novel patterning, which has been considered for some time, these have also progressed, and Direct Self Assembly and nanoimprint lithography have become popular in recent years. In this report, we explored the possibility of nanoimprinting for intermediate pitch hole patterns. We also studied the possibility of process collection, which has traditionally been believe to be unnecessary. We report the results of an investigation into what shapes and pitches are difficult to deal with using hole patterns. Secondly, we consider the process of creating mask templates and explain a new process for mask processing. Finally, we explain the alignment challenges and solutions that NIL faces in applying to cutting-edge devices. In this report, we will describe these issues and discuss the possibility of solutions using new methods and future strategies for mask processes.

Nano-imprint lithography (NIL) is a promising technique for nano-pattern fabrication of future semiconductor devices because it can easily transfer sub-20nm scale structures at room temperature. However, in semiconductor device manufacturing, the required level of throughput and defect is high, and it becomes a critical issue in the practical application of NIL. The major defects in NIL are various contaminations, non-fill defect of resists, and mold releasing failures which occur during mold releasing. Since non-fill defect can be improved by allowing sufficient time for resist spreading, there is a trade-off between throughput and non-fill defects. Release defect can also be improved by fluorine treatment of the mold surface or addition of a fluorine-based release agent in the resist, but these approaches suppress the resist spreading, so there is a trade-off between throughput and release defects. In this report, resist design to balance throughput and defects in Ink-jet (IJ) type UV-NIL process is investigated for semiconductor device manufacturing.

To further enhance fill time, we introduce the use of solvent diluted NIL resists. This is a significant departure from the standard NIL resists currently used that are monomer-based on contain no solvent. After ink-jetting the solvent rich resist, drop spreading is significantly enhanced, so that the amount of remaining trapped gas is minimized, therefore enhancing fill time. By applying a multi-field dispense strategy, the solvent has time to volatilize, leaving behind only the monomer-based resist material which can then be imprinted. The purpose of this paper is to review the performance improvements for NIL and report the demonstration of the fast-filling concept using a combination of a solvent diluted resist and a CO2 environment with a patterned mask that simulates actual devices. Additional topics to be discussed include patterning capability of the new resist, defectivity results and other pre and post processing steps.

For nanoimprint lithography (NIL), Optimization of NIL and Associated Pattern Transfer Processes for the Fabrication of Advanced Devices are further being developed. The optimization of both NIL patterning and pattern transfer methods has now been extended to address a simpler dual damascene process which is applicable to advanced logic devices. The work has now been extended to enable the entire dual damascene flow. Purpose of this paper is to describe the work done to enable the patterning of these structures.

Nanoimprint Lithography (NIL) is a technique for fabricating fine patterns by transferring a template's pattern onto a resist through physical contact. Template damage by particles remains a critical issue in NIL. However, the effect of particle characteristics on template damage have not been investigated. This study reveals that template damage is caused by shear force exerted by particles, and particles with higher Young's modulus are more likely to cause damage. Furthermore, particle sizes that causes template damage was investigated and it has been shown that the thicker Residual Layer can reduce template damage and increase particle size tolerance. The study aims to extend template life by investigating parameters influencing template damage and proposing mitigation methods.

Nanoimprint lithography, NIL, is attracting attention again as the next generation lithography. Its advantages of higher resolution to ArF-i lithography and lower cost-of-ownership and power consumption to EUVL are still sought for the development of sustainable semiconductor manufacturing technology. For years, we have developed E-beam written template and its replication technology by NIL simultaneously. In this presentation, we will report on our newly developed works that bring our template performance to the requirements of advanced device manufacturing from the aspects of resolution and defectivity.

This work addresses two key challenges in nanoimprint lithography (NIL): achieving sub-micron overlay alignment and analyzing high-refractive index (HRI) materials. Advanced scatterometry and SEM techniques are employed to evaluate HRI materials, ensuring precise pattern transfer and minimal defects. The study highlights improvements in overlay accuracy and material performance, both critical for applications in photonics and semiconductor industries. The combination of optimized overlay alignment and robust material characterization enables scalable, high-precision NIL processes for next-generation device fabrication.

Nanoimprint lithography or NIL is capable of transferring fine pattern and 3D pattern of a template onto a resist layer by physical contact in a single process step. Developing the complete ecosystem for essential requirements, such as, tool, resist and templates, we are at present, evaluating NIL’s potential as a low-cost patterning solution for the mass production of semiconductor devices. As part of our endeavor, we are developing methods for dust control on wafer. NIL template is prone to permanent damage by dust during physical contact with the resist on the wafer causing drastic increase in running cost. We have studied several countermeasures to overcome such issues and results of such studies would be presented.

Moving into the era of EUV lithography, it is becoming increasingly difficult for traditional chemically amplified resist materials to meet the patterning requirements. In view of this, there is growing interest in alternative resist platforms or auxiliary patterning techniques such as directed self-assembly (DSA). By combining EUV lithography with DSA, dense line/space or hexagonal contact hole patterns can be rectified. As such, DSA can enable the use of CAR materials at increasingly tight pitch and acceptable EUV dose. In this talk, we will firstly discuss the rectification of pitch 24 nm line/space patterns. It will be shown how line edge roughness can be minimized by optimizing the etch and stack. Furthermore, we will touch upon the use of high-chi DSA materials for further roughness reduction. Finally, efforts to control the pattern placement error for pitch 30 nm hexagonal contact hole arrays will be presented.

The integration of Directed Self-Assembly (DSA) of block copolymers (BCP) with Extreme Ultraviolet (EUV) lithography is gaining significant attention as a potential solution to the challenges associated with sub-21 nm patterning in semiconductor manufacturing. This study investigates the application of DSA in both low and high NA EUV lithography, with a focus on enhancing resolution and improving variability control. The performance of DSA is evaluated using EUV-printed guide patterns, examining the relationships between process window, defectivity, and variability (LER & LWR). Additionally, a comparative analysis is conducted on the quality of DSA-rectified patterns between PS-b-PMMA and high-χ block copolymers, along with the dry etch development of each system. Special attention is placed on the transition to high-NA EUV lithography, which offers increased resolution but requires thinner resists due to the reduced depth of focus. The findings suggest that DSA, in conjunction with EUV lithography, holds significant promise for next-generation lithography solutions.

Single exposure extreme ultraviolet (EUV) lithography advances further device feature scaling that replaces multi-patterning techniques with ArF immersion lithography. As the patterning requirements have been tightened by reduction of circuit dimensions, inhomogeneity inside conventional EUV photoresists such as chemically amplified resists present a technical challenges like dimensional non-uniformity and associated defects in EUV patterns, because EUV photons having a wavelength of 13.5 nm lead photon shot noise in EUV patterns. Directed self-assembly (DSA) is a well-known technology for rectifying the resist pattern quality printed by photolithography. Many studies have shown that EUV lithography combined with DSA using block copolymer can significantly mitigate the variability of stochastics from EUV lithography. In this study, we investigate the DSA rectification process for hexagonal contact hole patterns by developing and testing a newly designed BCP to achieve better rectification performance such as LCDU and placement error as compared to PS-b-PMMA which was used as a reference. We also examined the effect of material and process parameters for performance improvement.

EUV (Extreme Ultraviolet) lithography is susceptible to stochastic defects, making it challenging to ensure sufficient process margins. Although DSA (Directed Self-Assembly) is an existing lithography technology, it is considered a potential patterning solution. PS-b-PMMA is a representative DSA material, but the presence of high-chi materials is essential to support miniaturization. We aim to develop high-chi materials that are comparable to PS-b-PMMA in terms of process margins. In this paper, we discuss our DSA activities to date and our strategy for high-chi materials that could become the next generation of DSA materials.

In this paper, we describe newly developed high-chi block copolymers that can form equilibrium domain spacing (L0) as small as 12 nm. They are classified as silicon and carbon rich BCPs which show good DSA at 18 nm (5x multiplication), 24 nm (1:1 rectification), and 14 nm (2x multiplication) using thermal annealing under appropriate underlayer patterns. An optimum etch condition produced a complete removal of polar block without line collapse. We demonstrate rectification of the EUV line & space (L/S) patterns to smoothen the patterned lines to 0.9 ± 0.01 nm and 1.1 ± 0.01 nm of line-width roughness and line-edge roughness, respectively. A comparison of 24 nm EUV rectification DSA of PS-b-PMMA and the new high-chi BCP was performed, and the results are discussed.

The application of DSA (directed self-assembly) to semiconductor processes is expected to realize the repair of fine patterns made by existing lithography and the improvement of pattern density. The use of EUV (extreme ultra-violet), which has been widely used in recent years, can form fine patterns with a single exposure, which contributes to reducing the number of masks. However, since the pattern is formed with a smaller number of photons than conventional exposure, defects are likely to be generated stochastically, and further improvement is required to ensure sufficient process margin. In particular, in high-density hole patterns required for the capacitor layer of DRAM (dynamic random-access memory), suppressing the occurrence of missing defects and kissing defects is contradictory to reducing the exposure dose. Therefore, it is expected that a technology combining DSA and optical lithography can achieve both cost and pattern performance. In this presentation, we will show the hole pattern multiplication process using DSA and its future scalability, and report on our efforts to improve the fidelity of the pattern.

State of the art DRAM devices utilize crosshatch self-aligned quadruple patterning (X-SAQP) as the primary process method to create the contact hole (C/H) patterns of the capacitor array. However, X-SAQP requires many process steps resulting in long cycle times and added costs. In addition, SAQP suffers from line-wiggling and pitch-walking defects as the geometry size is scaled down. One cost effective alternative to X-SAQP is to apply directed Self-assembly (DSA) materials as a pattern pitch splitting method to significantly reduce the number of processing steps. DSA shows great promise at solving the CD variance problem that impacts SAQP at a much-reduced cost; however, being a radically different type of process, it has a separate set of failure modes—namely, Dislocation defect and Pattern Placement Error (PPE). In this study we review the progress of block copolymers (BCP) development for C/H patterns covering a range of pitch sizes in a DRAM device. First-generation BCP comprised of PS-PMMA block copolymers were limited in performance at larger pitch sizes due to the slower kinetics of the system. For large pitch CH layouts, the modified PS-PMMA BCP and the effect of kinetic

Area-selective deposition as a bottom-up approach provides a viable way to address patterning challenges in achieving high-precision pattern transfer and minimize edge placement error. Here we developed a method of area-selective deposition using a class of sequence-defined polymers as growth-promoters that enhance the nucleation and growth of metal oxides in vapor phase infiltration to selectively deposit aluminum oxide hard masks with high growth rates. Furthermore, we demonstrate the physicochemical property and therefore aluminum oxide uptake of the polymer growth-promoters can be tuned by incorporating different chemical groups at precisely defined compositions.

Polymer brushes, both patterned and unpatterned, are essential materials in DSA. Starting from the development of end-grafted polymer brushes to modify silicon substrate surface energies, to more universal approaches based on side-chain grafted polymer brushes to control the orientation of block copolymer domains, polymer brush chemistry has been instrumental in driving the DSA technology. However, large scale fabrication of brush grafted surfaces remains a challenge. I will present the latest advances in my group on a unconventional approach to fabricate polymer brushes and to use patterned polymer brushes to push the limits of DSA.

Flat optics present exciting opportunities for the miniaturization of many devices, but the achievable designs can be limited by the available materials. By expanding the library of available high-index materials that can be patterned at high-resolution, new flat optics designs can be realized. This talk will present results that leverage the CMOS tooling of imec’s pilot lines to pattern high-index materials for applications from the visible to the IR.

Optical devices such as AR-/VR-goggles, as well as new ways of realizing optical elements by the use of Metasurfaces, are being developed. These fast-emerging, and in some cases disruptive, technologies will be required in larger volumes. A cost-efficient way of manufacturing such devices is possible by using Nano-Imprint Lithography (NIL). The required patterns are created as a 2D or 3D profile on a master which is then used to imprint onto the actual device material or substrate. For some of the applications like metalenses, NIL might even be the only way to manufacture them in a timely and cost-effective manner. Therefore, the manufacturing of the NIL master becomes a critical aspect for the future development of such technologies. One way to provide high quality NIL masters is to apply photomask technology in a photomask manufacturing environment. The master will be made either on a 6-inch square Quartz substrate, or a 200mm Si wafer substrate. For quartz there is already a standard process available as a variety of photomask types require quartz etching. In the case of Si master, photomask patterning techniques are also used. The patterns on a NIL master for AR-/VR-devices

Displacement Talbot Lithography (DTL) introduces a disruptive approach to patterning high-resolution periodic structures, particularly for high-volume production of photonic devices. It is a mask-based, non-contact printing technique capable of producing structures at the highest resolution allowed by the used wavelength. The DTL concept brings all the proven benefits of optical lithography to high-resolution periodic patterning, without the high cost and complexity of projection systems.

In this presentation, I will talk about the advancements in monolithic 3D integration of emerging 2D field-effect transistors (FETs) as the cornerstone for next-generation sensing, memory, and logic devices. Our recent breakthroughs include the successful demonstration of wafer-scale 2-tier and 3-tier 3D integration, utilizing MoS2 and WSe2 FETs as foundational components. These innovations have opened new avenues for multifunctional circuits, offering significant potential for future electronic systems. In addition, I will present our research on bio-inspired neuromorphic computing, where we have leveraged the unique properties of 2D materials to design solid-state devices that exhibit low power consumption and mimic key biological processes. These devices emulate auditory processing in barn owls, collision avoidance in locusts, probabilistic computing in dragonflies, and multisensory integration in octopuses. By integrating 2D materials with bio-inspired architectures, our work establishes a robust platform for the development of highly compact and versatile integrated circuits within the revolutionary third dimension. The broader impact of these technologies has the potential

Thin films of Transparent Conductive Oxides (TCO) are used as electrodes or optical filters in display devices. While ITO (Indium Tin Oxide) usage is widespread today, alternative materials such as ZnO (Zinc oxide) or SnO2 (Tin dioxide) are promising, yet they remain challenging to pattern at the micrometer scale. Using the High Precision Capillary Printing (HPCaP) technology developped by Hummink, thin masking layers of polymers are printed on a Si sample before deposing a TCO layer by Atomic Layer Deposition (ALD). Removing the polymer yields the expected pattern with a pixel size smaller than 5 µm. Although not suitable for mass production, our approach shows promises for prototyping and repair of TCO-based display devices.

Advanced packaging (AP) operates on a spectrum balancing the cost and throughput against performance and density. Applied Material’s Digital Lithography Technology© (DLT)© brings an innovative exposure tool that addresses some of the unique photolithography challenges of AP manufacturing industry. Unlike traditional stepper, DLT© is a mask-less tool, equipped with digital micro-mirror device (DMD) in its imaging assembly that can resolve 2 um and 1 um lines-space (L/S) features with high aspect ratios, maintaining critical dimension uniformity (CDU) across entire panels. Our technology ensures precise overlay control even under challenging conditions, such as warped substrates and high local topography, all while sustaining high throughput. This capability positions us at the forefront of reshaping the industry's lithography roadmap.

This talk discusses the development and optimization of a high-resolution semi-additive process for RDL. We discuss our approach to obtain optimal resist sidewalls and fine lines on a contact aligner. Then we show the final plating results with little to no undercut post seed layer etch by using a novel wet etch.

Adhering to Moore's Law in the semiconductor industry has become increasingly challenging as higher chip densities demand significant financial investment and effort. To tackle these issues, the industry has shifted towards 3D heterogeneous integration, where multiple chip stacks are interconnected using through-silicon vias (TSVs). This approach focuses on system-level integration, improving performance while controlling costs. TSVs are crucial, enabling vertical connections that increase chip density and reduce the overall size of devices. However, metrology and inspection tools have lagged in supporting these advanced processes. To address this, a new Ultra-Fast Correlative CMP metrology method is proposed, combining phase-shifting interferometry (PSI) with active-probe atomic force microscopy (AP-AFM). Developed by nano analytik GmbH, this method leverages advanced scanning probe microscopy technology for precise measurements. PSI provides rapid surface analysis, while AP-AFM enhances accuracy in complex areas. This integrated approach overcomes traditional speed and resolution limitations, offering a powerful tool for advancing 3D heterogeneous integration.

Two-photon lithography, used to create intricate 3D structures, often struggles to achieve desired geometries due to process limitations. To address these challenges, we present a novel solution combining neural networks with a differentiable 3D lithography model. Using a U-Net architecture, we predict optimized dose distributions from target 3D structures. To evaluate the performance of the predicted dose distributions, they are processed by a differentiable digital twin of the lithography process, which models key physical steps such as point spread function convolution, chemical diffusion, and development. This hybrid data-driven and physics-based approach enables end-to-end training of the U-Net, achieving dose distribution designs for 3D structures. Our results demonstrate improved precision in two-photon lithography, offering enhanced control for advanced microscale manufacturing.

This presentation introduces methods for optimizing various direct-writing lithography systems from Heidelberg Instruments to push the resolution limit for smaller structures in collaboration with IMS Chips germany.

Metamaterial-based light manipulation is crucial for advancing optical imaging and sensing in various nanophotonic devices, such as optoelectronic sensors, optical nanoantennas, and neuromorphic sensors. Traditional 2D planar nanostructures utilize light interactions with metal and dielectric materials, but light coupling is limited to horizontal directions, restricting plasmon interactions. In contrast, quasi-three-dimensional (quasi-3D) metal-dielectric nanoarrays provide enhanced functionality by controlling light-matter interactions at the nanoscale. A key advantage of 3D nanostructures is the generation of additional resonance modes by combining upper and lower nanostructured arrays, enabling strong near-field confinement and optical amplification at resonance frequencies. This work focuses on designing and optimizing quasi-3D post arrays for better wavelength selectivity. These nanostructures enable plasmonic filters in the mid-infrared (MWIR) range, enhancing optical efficiency. Simulations show scalability and improved wavelength selectivity, contributing to advances in infrared imaging technology.

In the developing field of semiconductor quantum device fabrication one of the biggest challenges to face at present is the development of an appropriate lithography scheme. Because of the nanometric feature sizes and high feature density typical in semiconductor quantum devices, state of the art lithography will be needed. In this work, we propose the combination of top-down thermal scanning proble lithography (t-SPL) and bottom-up directed self-assembly (DSA) of block copolymers (BCP) as a suitable lithography process for the fabrication of these devices. The high overlay alignment accuracy inherent in t-SPL patterning and the pattern resolution improvement brought by the DSA of BCP has the potential to suffice the high resolution and high overlay alignment control necessary in semiconductor quantum device fabrication.

This research explores the dynamic assembly of colloidal particles using non-magnetic colloids mixed with magnetic nanoparticles. By modulating short-range attractions and long-range repulsions through depletants and external magnetic fields, we achieve and control various equilibrium and non-equilibrium states. Using Brownian dynamics simulations and Grand Canonical Monte Carlo methods, we identified key equilibrium structures, such as percolated gels and crystalline states. Beyond equilibrium, the study employs feedback control mechanisms and toggled potentials to navigate the system through kinetic traps, facilitating transitions from disordered to ordered states. A Model Predictive Control strategy, based on Markov Decision Processes, was also conceptualized to optimize assembly pathways in complex energy landscapes. This work advances our ability to design materials with precise structures, with potential applications in photonic crystals and drug delivery systems. The methodologies developed are expected to have a significant impact on colloidal assembly.

Patterns generated by the directed self-assembly (DSA) of block copolymers (BCPs) have been known for over 15 years to possess improved quality relative to their underlying topographical or chemical guiding patterns. Today, leading edge manufacturers of logic and memory devices are rushing to install expensive high-NA EUV lithography tools into their factories despite uncertainty in material selection, resist sensitivity, and pattern quality. DSA is a viable contingency option to remediate stochastic defects and RLS tradeoff effects. In the case of line-and-space patterns, the BCP is self-assembled atop a 1:1 guiding pattern. In this poster we aim to summarize our recent efforts to create and study such a DSA rectification flow at the Albany NanoTech Complex clean room facilities, using lamella-forming poly(stryrene-block-methyl methacrylate). We will describe the impact of process effects on defects and LER/LWR for 28 nm pitch line and space patterns generated by 0.33 NA EUV, as a model demonstration we can expect to extend to High-NA EUV patterns.

We have previously used KrF excimer laser to directly process fine through-vias and have achieved the formation of vias with a diameter of 15 µm in glass thickness of 500 µm. In order to achieve high productivity, we used Diffractive Optical Element (DOE) to perform simultaneous multi-point glass processing. In this study, we achieved simultaneous processing of 99 vias using KrF excimer laser and DOE. As these results, it is possible to achieve 1,000 vias/sec with glass thickness of 500 µm.

Whereas standard CMOS processes are classically done on silicon substrates, new optical applications require the use of glass substrates. This can be achieved by transferring processes initially done on silicon substrates onto glass substrates or by performing processes directly on glass substrates. This paper deals with the development of photolithography directly on glass wafer. In a first part, we will present the different problematics we have been facing by using standard photolithographic processes on glass substrate and we will show that all these problematics are mainly due to thermal different behavior of a glass substrate compared to a silicon substrate. In a second part, we will detail the thermal study we did on different types of glass substrate at wafer surface when processing different lithographic bakes and demonstrate that glass wafer undergo warpage during bake and cooling steps and that this warpage is responsible for bad temperature uniformity at wafer surface and consequently in the resist film. We will finally see that thanks to photolithographic process optimization we have been able to achieve good photolithographic performances on glass wafer.

Strict specifications of local critical dimension uniformity (LCD) and line edge roughness (LER) on the leading-edge mask fabrication promote wide use of the lower sensitivity resist for electron beam lithography. This is because the higher exposure dose for the patterning mitigates the shot noise effect, which is the statistical position variability of electrons given by the beam shots. As the exposure dose increases and the beam current increases in order to retain the writing time, the resist heating effect appears as the degradation of LCDU due to the temperature-dependence of the resist sensitivity in the multi-beam mask (MBM) writers as well as the variable-shaped beam (VSB) mask writers. In this report, we will discuss the behavior of resist heating effect in MBM, and modeling for the correction.

Curvilinear formats store straight lines as polygonal segments, while curved parts are encoded as a set of control points, following the formalism of Bézier curves or B-Splines. These formats have been proposed by multibeam mask-writers, and a work group was formed to extend the Oasis format, retaining four types of curves. Among them, Implicit Bézier and B-Splines are of special interest, due to their compactness and potential for file conversion and geometric operations. For instance, sizing-like operations are not straightforward on B-Splines, as the curve doesn't pass through its control points. This paper presents different methods to move a point on a B-Spline to a desired location, discussing their advantages and disadvantages.

Nanoimprint Lithography has moved from purely academic interest to industrial relevance for the last decades and enabled the miniaturization of devices in fields of life science, optics and photonics applications. In this presentation, we will show how a single NIL resist material, the mr-NIL210 series, enables NIL to address the whole process window of photonic patterns manufacture, i.e. from diffractive nano optics to refractive micro optics. We will highlight examples where the mr-NIL210 series was used to replicate meta lens patterns (down to sub 100 nm), diffractive gratings (few 100 nm) as well as free form micro optics (micrometer scale). This broad application window of mr-NIL210 provokes commercial footprint and hence paves the way for NIL users to realize applications in the fields of AR/VR, MLAs, but also life science.

Nanoimprint lithography (NIL) allows faithful pattern transfer from mold (template) patterns and is expected to be effective for complex patterns such as mixture of L/S and via patterns for interconnects. In this work, we demonstrate complex L/S and via patterning for damascene interconnects using NIL. Mixed patterns of high density L/S lines and partially distributed vias with the half-pitch of 32 nm were perfectly patterned by NIL. Although there were via missing problem caused by the mold in the HP of 24 nm, we finally succeeded in patterning the complex mixed L/S and via layout at HP 24 nm using a mold obtained by an improved mold fabrication process.

Gray-scale lithographic nanofabrication techniques, including gray-scale interference lithography using patterned secondary exposure, gray-scale etching and thin-film deposition using ultrafine metal masks, etc. are demonstrated to fabricate spatially varying nanostructures over wafer-scale areas. These techniques can benefit the development of metasurfaces, structural coloration, optical filters, etc.

Curvilinear masks have demonstrated benefits over Manhattan masks for improved wafer process window and mask rules compliance (MRC). The reduced barriers of curvilinear mask manufacturing enabled the deployment of complex curvilinear masks from advanced computational lithography solutions like inverse lithography technology (ILT). ILT is known for its advantage of creating a patterning-optimized curvilinear mask through field operations. To maximize the benefits of ILT, it is beneficial to study the manufacturability of curvilinear masks. In this paper, we will present the results of curvilinear mask manufacturability studies using a specially designed set of parametric curvilinear patterns layout. Mask Error Correction (MEC) will be applied to evaluate its impact on mask manufacturability, and MRC rules will be evaluated in important metrics and their correlations to different feature types. Curvilinear masks created from ILT with different MRC rules, pattern fidelity control at corners and coverage of model-based assist features (MBAF) will be studied . The correlation between wafer performance and curvilinear ILT mask complexity will also be presented in the paper.

“Enhancing Lithographic Process Latitude: A Powerful Approach Using Inverse Lithography Technology for Depth of Focus Improvement” Yen-Lung Lua, Szu-Ping Chena, Chi-Neng Linb, Eric Huanga, Chun-Cheng Liaoa aNanya Technology Corporation, No. 98, Nanlin Rd., Taishan Dist., New Taipei City 243089, Taiwan R.O.C. ; bCadence Design Systems, 8F, No. 2, Lixing 6th Rd, East Dist, Hsinchu City, Taiwan R.O.C This article will present a comprehensive analysis of how ILT-generated masks can adjust the aerial image to enhance DOF, reducing the impact of focus variations on critical dimension uniformity. The proposed ILT approach is validated through simulation and experimental results, showing a significant increase in the process tolerance compared to conventional OPC methods. The improved DOF achieved with ILT not only enhances pattern fidelity but also contributes to the overall robustness and yield of semiconductor manufacturing. These findings demonstrate the efficacy of ILT in addressing DOF limitations, highlighting its role as a critical tool for future lithographic advancements.

In this study, a SiNx nanoporous membrane filter is fabricated on a 6-inch Si wafer by combining nanoimprint lithography and photolithography. To achieve dual-side alignment between the nanopore area and the template, nanopore patterning is conducted on the front side using nanoimprinting, followed by photolithography on the back side. This offers reliable throughput for mass production while ensuring precise pore size control and a narrow size distribution. The fabricated filter is applied to isolate exosomes from bovine milk, with Electrophoretic Oscillation (EO) introduced into the TF-DU method to enhance the exosome filtration efficiency by preventing blocking of the nanopores. The isolated exosomes maintain their physical and biological properties, with a mean particle size of approximately 110 nm, showing that they preserved spherical shape without any distortion or deformation. The photolithography-integrated nanoimprinting method for the fabrication of the nanofilter can provide a highly scalable and cost-effective solution for mass production.

Moore’s Law predicts ongoing critical dimension (CD) shrinking in integrated circuits, pushing lithographic processes to their limits. Traditional methods (EUVL, EBL, and NIL) face challenges like either low throughput or high costs. Here we introduce a novel hybrid approach, coined Faraday lithography (FL), which uses electric fields for precisely printing aerosol nanoparticles and subsequently etch away the rest of materials for patterning. The printing technique achieves a minimum line-width of 14 nm and is experimentally proven for wafer-scale fabrication. The printed metal features served as hard masks, realizing considerable reduction in CDs. One example for this is that we obtained straight lines of excellent LER with a width of only 1/10 to that of groove (space of line/space pattern) patterns, which were made from the lithographic processes. We also show that the FL can expand the patterns from 1D to 3D. This promising solution is therefore expected to advance semiconductor technologies and to even break boundaries set by the current mainstream lithography.

In DRAM (Dynamic Random-Access Memory) manufacturing, critical layers such as the high-density capacitor hole array and the bit-line periphery (BLP) with Storage Node Landing Pad (SNLP) pose significant challenges due to their complex patterning requirements. The capacitor hole array is crucial for DRAM performance, while the BLP layer involves intricate bi-directional line/space (L/S) designs. As DRAM technology transitions to EUV (Extreme Ultraviolet) lithography, single exposure solutions are sought to replace multi-mask processes, introducing challenges in maintaining resolution and reducing patterning time. This study explores how the method enhances pattern accuracy and shortens processing time in critical DRAM layers, particularly the capacitor hole array and bit-line periphery layers. Additionally, we investigate EUV-specific effects such as thru-slit and flare effects in memory data handling, which introduce further complexities in the patterning process. Experimental results indicate that the memory OPC flow not only resolves the long runtime issues of EUV OPC but also maintains high patterning accuracy, providing a reliable foundation for future DRAM manufacturing.

Carbon nanotube (CNT) arrays, critical for electron emission applications, benefit from precise spacing to minimize screening effects. Conventional lithography techniques face limitations in scalability and resolution for defining CNT array catalyst regions. This study leverages two-photon polymerization to achieve rapid, maskless patterning of sub-micron structures, offering enhanced precision and 3D design flexibility. Optimizing hatch pattern block spacing through a fractional factorial Design of Experiments (DOE) approach, key parameters such as infill density, illumination power, and contact area were tuned to improve liftoff efficiency by minimizing polymer-substrate interaction. Statistical Process Control (SPC) and Analysis of Variance (ANOVA) were employed to ensure batch-to-batch consistency. Metrology techniques, including Scanning Electron Microscopy (SEM), Atomic Force Microscopy (AFM), and Energy Dispersive X-ray Spectroscopy (EDS), confirmed critical dimensions and material composition. These advancements address challenges in lithography scalability and precision for semiconductor manufacturing applications.

Inorganic LED technology is becoming essential for high-performance AR/VR displays, a key to realizing the "Metaverse." While micro-scale inorganic LEDs have been extensively researched, they become more cost-effective and attractive at the nano-scale. This study demonstrates the fabrication of nano-scale inorganic LEDs using nanoimprinting lithography (NIL), a low-cost, high-throughput technique. About 267 million fin-LEDs, each measuring 4.0 x 0.7 μm² with a height of 1.1 μm, were created on a 4-inch blue GaN wafer. These fin-LEDs showed minimal variation in both length and height and were successfully integrated into electroluminescent (EL) devices using dielectrophoresis (DEP) technology. The study highlights the potential of fin-LEDs in future high-performance nano-scale inorganic LED displays.

In holographic systems such as AR and VR devices, the holographic grating is known to increase the efficiency by providing a slant angle. The Interference lithography system is essential for the high-quality production of slant gratings. However, there is a restriction on the angle of the slant structure fabricated by conventional dry interference lithography. Interference lithography with a pitch of 300 nm cannot achieve a slant angle of more than 22 degrees due to the geometrical limit of rays. We report on a novel system which combines a prism and immersion lithography to achieve a larger slant angle. A slant angle of 40 degrees can be realized with interference lithography at a pitch of 300 nm. We will present its mechanism and processing examples.

In holographic systems, such as AR and VR, holographic gratings with a slant angle are known to improve system efficiency. We developed an interference exposure system capable of fabricating slanted gratings with a controllable slant angle. To maintain exposure quality, traditional systems use low-power continuous wave UV light, leading to prolonged exposure times and reduced throughput. By employing a short-pulse laser with a wavelength of 355 nm and a pulse duration of 10 ns, we reduced exposure time but encountered challenges with coherence length, leading to insufficient beam size. To address this, we used an etalon to narrow the linewidth to 0.01 nm, achieving a coherence length of 12.6 mm, sufficient for exposure quality. We expect this approach to enhance throughput by approximately 100 times. This presentation discusses the results and improvements in throughput using the constructed interference optical system.

Curvilinear MRC Solution Yen-Lung Lu a , Anwei Liu b , Alan Zhu b , Hung Yu Lin c , Teng-Yen Huang a , Ya-Chieh Laia b , Chun- Cheng Liao a a Nanya Technology Corporation, No. 98, Nanlin Rd., Taishan Dist., New Taipei City 243089, Taiwan R.O.C.; b Cadence Design Systems, 2655 Seely Ave, San Jose, CA 95134, US ; c Cadence Design Systems, 8F, No. 2, Lixing 6th Rd, East Dist, Hsinchu City, Taiwan R.O.C ABSTRACT The continuous scaling of semiconductor technology nodes has driven the industry towards the adoption of curvilinear mask patterns, which offer enhanced pattern fidelity and process robustness compared to traditional Manhattan geometries. However, these curvilinear designs introduce significant challenges in mask synthesis, particularly in Mask Rule Check (MRC). Traditional MRC techniques, optimized for rectilinear patterns, struggle to accommodate the complex curvature and intricacies of curvilinear shapes, leading to suboptimal pattern fidelity and process windows. This article will present a novel curvilinear MRC framework that leverages advanced computational lithography techniques.

In interference lithography both reflective and refractive beam combiners are used. Due to the achromatic nature of reflection, the angle of reflection and the angle between two interfering waves are identical irrespective of wavelengths related to spectral bandwidth of the laser leading to the generation of fringes of unequal fringe width. Whereas, for a diffractive beam combiners the longer wavelength is bent more than that of the shorter wavelength maintaining the ratio of wavelengths to half the semi angles between the two interfering waves same for all the wavelengths leading to generation of fringes of the same special frequency. In present work theoretical and experimental investigation on design and analysis of a dual aperture holographic diffractive beam combiner is presented for the fabrication of evenly periodic fringe pattern of high spatial frequency irrespective of wavelengths associated with spectral bandwidth of laser source.

In this work we show how holograms can be used for maskless patterning using a simple optical setup. We first generate 10-bit multiphase time-multiplexed Fourier holograms of the ISO-12233 binary target pattern and then display them on phase-modulating LCOS SLMs using a 405 nm laser. Using a plano-convex lens of 75 mm focal length to perform optical Fourier transforms, these holograms can reconstruct target patterns for lithography. We compare reconstructions produced by a single SLM with those produced by displaying holograms on two SLMs in parallel operation. The two-SLM method produces replay fields with lesser blur, brighter illumination and 11.5% higher SNR. By spatially filtering un-diffracted light at the zeroth order and selecting a functional region of interest we can use these reconstructions for patterning and lithography. As a diffractive phenomenon, holography promises greater control on electric fields. This includes promises such as OPC-free resolution improvements. Such advances may allow this method to perform sub-μm scale lithography efficiently in future.

Volumetric additive manufacturing technologies have solved translations between 3D object and image spaces for rapid fabrication in homogeneous, high viscosity resin without layering or support structures. Parallax manufacturing (PM) expands these capabilities by introducing a fourth dimension of address. PM rapidly moves an optical toolhead above a flat slab of photosensitive resin that addresses resin voxels with individually controlled beamlets tilted in two angles. This approximately squares the number of beams that intersect at each voxel, dramatically increasing the solution space available to the optimization algorithm. The resin slab used in PM is unlimited in transverse extent, allowing for large area fabrication. In contrast, the transverse size of the computed axial lithography cylinder must be equal to its depth which is limited to several cm by diffraction. This architecture importantly utilizes a translation geometry that matches established manufacturing platforms including assembly lines, CNC machine tool beds and roll-to-roll processing.

We introduce a scanning one photon direct write tool that exposes the entire thickness of a thick photoresist in one pass to create complex 3D structure at orders-of-magnitude greater rate than existing techniques. As it is scanned above the resist, the objective lens projects light from a DMD spatial light modulator into a pixelated high NA light cone that continuously changes. Each voxel of the photoresist receives an integrated dose from hundreds of different light cones, exceeding the threshold dose inside a desired 3D volume while remaining below threshold in the design exterior. The set of light cones is found by numerically solving an inverse problem. In comparison to the currently used multilayer approach, this method exposes a single thick layer of photoresist in a single pass of the objective lens and is thus much higher speed, has no layering artifacts, and can create a larger range of structures.

For integrated circuits (ICs) fabrication, challenges arise due to the technological constraints of downsizing, interconnections, and materializing these components. Nanoscale 3D printing emerges as a promising solution to these challenges. At Aerosol Intelligence Lab (AIL), we have developed a method to print nanoparticles into expansive arrays of intricate 3D nanoarchitectures using “lines of forces”. We coined this technique as “Faraday 3D Printing”, inspired by Faraday’s lines, which are here repurposed as 3D nanodrawing tools. Such tools have no downsizing limit, heralding a horizon for atomic-level manufacturing. By adeptly manipulating electric and flow fields, we attain remarkable flexibility in multi-material and large-area printing, all while ensuring a high precision. This technology offers the capability to tailor optical, electronic, and mechanical attributes by modifying the material, geometry, feature size, and array periodicity of the printed nanoarchitectures. We contend that the outcome of Faraday 3D Printing signals a monumental paradigm shift, setting the future research agenda of AIL (more details can be found at www.jcfenglab.com).

In this paper, high dynamic grey–level overlap between the fields at different gradients is investigated and the influence of the negative–tone materials and the exposure dynamics is reviewed. The “cross–fade” technology is implemented in a manner that formerly unused regions of the exposure field act as a finely formed overlap gradient, forming a resolution wise crisp, but amplitude–wise smoothly diminishing border region that is exactly matched to its opposite counterpart. Optical microscopy, profilometry as well as scanning electron microscopy (SEM) of final process results and cross–sections were examined and compared. Firstly, the standard, negative tone resist was patterned by using this new feature. The experiment is transferred to the high-resolution polyimide dielectric material (Fujifilm LTC–9300 Series) digital patterning. In was proven, that also for dielectric materials, the Wide-Xfade functionality together with well controlled polyimide–dynamics is a critical feature that overcomes challenges of reticle limitations as found in steppers and enable stitchless “infinite”–field exposures in digital exposure like the EVG’s LITHOSCALE® system for advanced packaging.

The successful rollout of initial EUV scanners for mass production, combined with the recent ramp-up of high-NA tools, has sparked extensive research into EUV materials. Additionally, there is increasing interest in exploring hyper-NA systems to further advance device scaling. Despite these technological strides, the journey towards future technology nodes faces major challenges, especially concerning photoresists. Factors such as mask roughness, photon shot noise, process variability, and the intrinsic properties of resist materials pose significant hurdles. I will address some of these challenges and propose potential solutions to overcome them. I will present our recent results, demonstrating achievements down to 5 nm half-pitch, achieving a new record in photolithography. Moreover, I will introduce our in-house resist development endeavor, where we have formulated a groundbreaking metal-organic resist framework.

In this talk I will describe progress towards novel patterning technology for semiconductor manufacturing that synergizes extreme ultraviolet (EUV) lithography, block copolymers (BCPs), and DNA origami. We use EUV lithography to provide guiding patterns for BCP assembly, which multiplies the pitch. We then employ DNA origami to further multiply the pitch and enable sub-nanometer precision patterning. Our approach combines the strengths of each technique: EUV's industrial scalability, BCPs' self-assembly properties, and DNA origami's programmability and precision. We aim to surpass existing approaches in precision and programmability, potentially achieving arbitrary patterns beyond parallel lines. I will discuss challenges in optimizing DSA processes for multi-wafer scale production, implementing complex patterns, and meeting semiconductor industry yield and speed requirements. We are exploring pattern transfer techniques and seeking collaborations for EUV process testing and custom surface chemistry development.

Block copolymer (BCP) self-assembly creates periodic sub-100 nm nanostructures nm with high scalability. When combined with advanced lithography like extreme ultraviolet (EUV) lithography, it enhances patterning resolution and critical dimension uniformity. Meanwhile, BCPs can be block-selectively hybridized with inorganic elements via vapor-phase infiltration (VPI), a method derived from atomic layer deposition, eventually transforming BCP patterns into functional inorganic nanostructures. However, successful VPI requires effective chemical binding between precursors and BCP blocks, which can be challenging with less reactive precursors. Alumina priming, using trimethylaluminum (TMA), is commonly employed to increase precursor reactivity, enabling the VPI synthesis of various inorganic materials. This study explores the effects of alumina priming on ZnO nanostructures, fabricated via VPI in lamellar-patterned poly(styrene-b-methyl methacrylate) (PS-b-PMMA) BCP films. It evaluates how TMA exposure times impact the structural, compositional, and electronic properties of ZnO, offering insights for optimizing VPI in BCP thin films for patterning electrically functional metal oxides.

The successful application of block copolymer (BCP) directed self-assembly (DSA) for reducing pattern roughness (i.e., line and width) associated with Extreme Ultraviolet Lithography requires minimal self-assembled defectivity and smooth pattern features, requiring BCP systems that are weakly and strongly segregated, respectively. This talk will present a potential solution to this dilemma using a two-step annealing process for engineering assembly pathways using neat BCPs and BCP/homopolymer blend systems. The first step involves annealing in a solvent with near neutral selectivity to both BCP blocks resulting in a weakly segregated BCP system allowing for rapid self-assembly with low defectivity. In the second step the samples are thermally annealed to enable short-range polymer chain rearrangement that sharpens domain interfaces under strong segregation conditions. Process windows across a range of blend compositions and annealing conditions that maximize assembly kinetics and minimize pattern roughness are identified.