San Jose Convention Center
San Jose, California, United States
25 February - 1 March 2018
Conference 10588
Design-Process-Technology Co-optimization for Manufacturability XII
Wednesday - Thursday 28 February - 1 March 2018
Important
Dates
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Abstract Due:
28 August 2017

Author Notification:
26 October 2017

Manuscript Due Date:
31 January 2018

Conference
Cosponsors
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Conference
Committee
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Conference Chair
Conference Co-Chair
Program Committee
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Additional Conference
Information



Conference Chair:
Jason P. Cain
Advanced Micro Devices, Inc. (USA)





Conference Co-Chair:
Chi-Min Yuan
NXP Semiconductors (USA)
Wednesday 28 February Show All Abstracts
Session 1:
Trends in DPTCO
Wednesday 28 February 2018
8:00 AM - 9:40 AM
Location: Room 211
Session Chairs:
Jason P. Cain, Advanced Micro Devices, Inc. (United States) ;
Chi-Min Yuan, NXP Semiconductors (United States)
Using machine learning at the leading edge (Keynote Presentation)
Paper 10588-1
Author(s): David Greenlaw, NVIDIA Corp. (Germany)
Show Abstract
Efficient place and route enablement of 5-tracks standard-cells through EUV compatible N5 ruleset
Paper 10588-2
Author(s): Luca Mattii, Technische Univ. Braunschweig (Germany), Cadence Design Systems, Inc. (United States); Vassilios Gerousis, Cadence Design Systems, Inc. (United States); Mladen Berekovic, Technische Univ. Braunschweig (Germany); Peter Debacker, Syed Muhammad Yasser Sherazi, Dragomir Milojevic, Rogier Baert, Julien Ryckaert, Ryan Ryoung-Han Kim, Diederik Verkest, Praveen Raghavan, IMEC (Belgium)
Show Abstract
Patterning method impact on sub-36nm pitch interconnect variability
Paper 10588-3
Author(s): Nicholas V. LiCausi, GLOBALFOUNDRIES Inc. (United States); James H.-C. Chen, IBM Research (United States); E. Todd Ryan, R.S. Smith, GLOBALFOUNDRIES Inc. (United States)
Show Abstract
Applying machine learning to pattern analysis for automated in-design layout optimization
Paper 10588-4
Author(s): Jason P. Cain, Moutaz Fakhry, Advanced Micro Devices, Inc. (United States); Piyush Pathak, Jason Sweis, Frank Gennari, Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)
Show Abstract
Session 2:
Pattern Correction Methods: Joint session with conferences 10588 and 10587
Wednesday 28 February 2018
10:30 AM - 12:10 PM
Location: Room 210C
Session Chairs:
Neal V. Lafferty, Mentor, a Siemens Business (United States) ;
Carlos Fonseca, Tokyo Electron America, Inc. (United States)
Model-based cell-array OPC for productivity improvement in memory fabrication
Paper 10587-21
Author(s): Ahmed Seoud, David Wang, Mentor Graphics Corp. (United States); Jebum Yoon, Boram Jung, Mentor Graphics (Korea) LLC. (Korea, Republic of); Sang-Jin Oh, Byoung-Sub Nam, Se-Young Oh, Chan-Ha Park, SK Hynix, Inc. (Korea, Republic of); Hyun-Jo Yang, SK Hynix, Inc. (United States)
Show Abstract
Optimization of optical proximity correction to reduce mask write time using genetic algorithm (GA)
Paper 10588-5
Author(s): Gregory J. Dick, Abhishek Asthana, Liang Cao, Jing Cheng, David Power, GLOBALFOUNDRIES Inc. (United States)
Show Abstract
Model-assisted template extraction application to contact hole patterns in high-end flash memory device fabrication
Paper 10587-22
Author(s): Ahmed Seoud, Le Hong, Yuansheng Ma, Mentor Graphics Corp. (United States); Gyu-Yeol Chae, Jeong-Woo Lee, Mentor Graphics (Korea) LLC. (Korea, Republic of); Dae-Jin Park, Hyoung-Soon Yune, Se-Young Oh, Chan Ha Park, Hyun-Jo Yang, SK Hynix, Inc. (Korea, Republic of)
Show Abstract
Advanced rules-based corrections strategies and their application for master manufacturing and replication on the 200mm wafer scale SmartNIL process
Paper 10588-6
Author(s): Hubert Teyssedre, Jacky Chartoire, Patrick Quemere, Maryline Cordeau, Loïc Perraud, Stéfan Landis, Jérôme Hazart, Laurent Pain, CEA Grenoble (France)
Show Abstract
Rigorous ILT optimization for advanced patterning and design-process co-optimization
Paper 10587-23
Author(s): Kosta Selinidis, Guangming Xiao, Hongyuan Cai, Amyn Poonawala, Aran Kazarian, Peter Brooker, Kevin Lucas, Synopsys, Inc. (United States)
Show Abstract
Lunch/Exhibition Break 12:10 PM - 1:30 PM
Session 3:
Design-Technology Co-optimization
Wednesday 28 February 2018
1:30 PM - 3:10 PM
Location: Room 211
Session Chairs:
Ru-Gun Liu, Taiwan Semiconductor Manufacturing Co. Ltd. (Taiwan) ;
Vivek K. Singh, Intel Corp. (United States)
Pre-PDK block-level PPAC assessment of technology options for sub-7nm high-performance logic (Invited Paper)
Paper 10588-7
Author(s): Lars W. Liebmann, GLOBALFOUNDRIES Inc. (United States); Vassilios Gerousis, Paul Gutwin, Cadence Design Systems, Inc. (United States); Gregory Northrop, Marco Facchini, Lionel Riviere, Jason Stephens, Zachary Baum, Norihito Nakamoto, Daniel Chanemougame, Geng Han, GLOBALFOUNDRIES Inc. (United States)
Show Abstract
Track height reduction for standard-cell in below 5nm node: How low can you go?
Paper 10588-8
Author(s): Syed Muhammad Yasser Sherazi, Peter Debacker, IMEC (Belgium); Luca Mattii, Cadence Design Systems, Inc. (United States); Praveen Raghavan, IMEC (Belgium); Vassilios Gerousis, Cadence Design Systems, Inc. (United States); Diederik Verkest, Anda Mocuta, Ryan Ryoung Han Kim, Alessio Spessot, Julien Ryckaert, IMEC (Belgium)
Show Abstract
A compact multi-bit flip-flop with smaller height implementation and metal-less clock routing
Paper 10588-9
Author(s): Jaewoo Seo, SAMSUNG Electronics Co., Ltd. (Korea, Republic of), KAIST (Korea, Republic of); Jinwook Jung, Youngsoo Shin, KAIST (Korea, Republic of)
Show Abstract
DTCO exploration for efficient standard cell power rails
Paper 10588-10
Author(s): Bharani Chava, Julien Ryckaert, Luca Mattii, Syed Muhammad Yasser Sherazi, Peter Debacker, Alessio Spessot, Diederik Verkest, IMEC (Belgium)
Show Abstract
Session 4:
Layout Optimization
Wednesday 28 February 2018
3:40 PM - 5:00 PM
Location: Room 211
Session Chairs:
Luigi Capodieci, KnotPrime, Inc (United States) ;
Michael L. Rieger, Consultant (United States)
Post-decomposition optimizations using pattern matching and rule-based clustering for multi-patterning technology
Paper 10588-11
Author(s): Lynn T.-N. Wang, Sriram Madhavan, GLOBALFOUNDRIES Inc. (United States)
Show Abstract
Pin routability and pin access analysis on standard cells for layout optimization
Paper 10588-12
Author(s): Jian Chen, Semiconductor Manufacturing International Corp. (China); Hua Ding, Cadence Design Systems, Inc. (China); Wei Xu, Shuai Li, Cadence Design Systems, Inc. (United States); Shengrui Qu, Cadence Design Systems, Inc. (China); Jo Wang, ChengYu Zhu, Semiconductor Manufacturing International Corp. (China); Ya-Chieh Lai, Cadence Design Systems, Inc. (United States); Miao Liu, Cadence Design Systems, Inc. (China)
Show Abstract
Variability-aware double-patterning layout optimisation for analog circuits
Paper 10588-13
Author(s): Yongfu Li, Valerio Perez, Zhao Chuan Lee, Vikas Tripathi, GLOBALFOUNDRIES Singapore (Singapore); I-Lun Tseng, GLOBALFOUNDRIES Singapore Pte. Ltd. (Singapore); Jonathan Yoong Seang Ong, GLOBALFOUNDRIES Singapore (Singapore)
Show Abstract
Litho-friendly ViaBar insertion with InDesign AutoFix flow
Paper 10588-14
Author(s): Ahmed Elsemary, GLOBALFOUNDRIES Inc. (United States); Moutaz Fakhry, Jason P. Cain, Advanced Micro Devices, Inc. (United States); Ahmed Mohyeldin, Janam Bakshi, Mohamed Ismail, Nishant Shah, Karthik Krishnamoorthy, Uwe Paul Schroeder, GLOBALFOUNDRIES Inc. (United States)
Show Abstract
Session PS1:
Posters-Wednesday
Wednesday 28 February 2018
5:30 PM - 7:30 PM
Location: Hall 2

Posters will be on display from 10:00 am to 5:00 pm, and again from 5:30 pm to 7:30 pm during the poster session. Come to view the high-quality papers that are presented in this alternative format, and interact with the poster authors who will be present during the poster session. Enjoy light refreshments while networking with your colleagues.

Full author or technical registration is required for entry to the poster session. Please wear your registration badge.
Timing optimization in SADP process through wire widening and double via insertion
Paper 10588-26
Author(s): Youngsoo Song, SAMSUNG Electronics Co., Ltd. (Korea, Republic of); Jinwook Jung, KAIST (Korea, Republic of); Daijoon Hyun, SAMSUNG Electronics Co., Ltd. (Korea, Republic of); Youngsoo Shin, KAIST (Korea, Republic of)
Show Abstract
Characterization of metal line-width variation in via first dual-damascene approach and its modeling using machine learning artificial neural network algorithms
Paper 10588-27
Author(s): Pietro Cantu, STMicroelectronics (Italy); Chiara Catarisano, STMicroelectronics SRL (Italy); Nicoletta Corneo, Emma Litterio, Benedetta Triulzi, STMicroelectronics (Italy)
Show Abstract
Cross-MEEF assisted SRAF print avoidance approach
Paper 10588-28
Author(s): Vlad Liubich, William Brown, George Lippincott, Eric Martinson, James Word, Mentor, a Siemens Business (United States)
Show Abstract
A weak pattern random creation method for lithography process tuning
Paper 10588-29
Author(s): Meili Zhang, Guogui Deng, Mudan Wang, Shirui Yu, Shanghai Huali Microelectronics Corp. (China); Xinyi Hu, Chunshan Du, Qijian Wan, Mentor Graphics Corp. (China); Aliaa Kabeel, Kareem Madkour, Mentor Graphics Egypt (Egypt); Wael Manhawy, Joe Kwan, Mentor Graphics Corp. (United States)
Show Abstract
Pattern-based IP block detection, verification, and variability analysis
Paper 10588-30
Author(s): Muhamad Asraf Ahmad Ibrahim, Mohamad Fahmi Muhsain, Ezni Aznida Kamal Baharin, Silterra Malaysia Sdn. Bhd. (Malaysia); Jason Sweis, Ya-Chieh Lai, Philippe Hurat, Cadence Design Systems, Inc. (United States)
Show Abstract
A smart way to extract repeated structures of a layout
Paper 10588-31
Author(s): Fang Wei, Tingting Gu, Zhihao Chu, Chenming Zhang, Han Chen, Jun Zhu, Shanghai Huali Microelectronics Corp. (China); Xinyi Hu, Chunshan Du, Qijian Wan, Mentor Graphics Corp. (China)
Show Abstract
Using pattern-based layout comparison for a quick analysis of design changes
Paper 10588-32
Author(s): Qijian Wan, Mentor Graphics Corp. (China); Lucas Huang, Legender Yang, Huan Kan, Elaine Zou, Semiconductor Manufacturing International Corp. (China); Chunshan Du, Xinyi Hu, Mentor Graphics Corp. (China)
Show Abstract
An efficient way of layout processing based on calibre DRC and pattern matching for defects inspection application
Paper 10588-33
Author(s): Qijian Wan, Mentor Graphics Corp. (China); Helen Li, Robben Li, Tyzy Lee, Teddy Xue, Hermes Liu, Hall Wu, Semiconductor Manufacturing International Corp. (China)
Show Abstract
Leverage calibre pattern matching to address SRAM verification challenges at advanced nodes
Paper 10588-34
Author(s): Qijian Wan, Mentor Graphics Corp. (China); Huan Kan, Lucas Huang, Legender Yang, Elaine Zou, Semiconductor Manufacturing International Corp. (China); Chunshan Du, Xinyi Hu, Yu Zhu, Mentor Graphics Corp. (China); Elven Huang, Jonathan Muirhead, Recoo Zhang, Mentor Graphics Corp. (United States)
Show Abstract
A portable pattern-based design technology co-optimization flow to reduce optical proximity correction run-time
Paper 10588-35
Author(s): Yi Chieh Chen, Cadence Design Systems, Inc. (Taiwan); Ya-Chieh Lai, Philippe Hurat, Cadence Design Systems, Inc. (United States); Hung-Yu Lin, Cadence Design Systems, Inc. (Taiwan)
Show Abstract
Hybrid hotspot library building based on optical and geometry analysis at early stage for new node development
Paper 10588-36
Author(s): Ying Chen, Xiaojing Su, Lijun Zhao, Yayi Wei, Yajuan Su, Tianchun Ye, Institute of Microelectronics (China)
Show Abstract
Thursday 1 March Show All Abstracts
Session 5:
Design Interactions: Joint session with conferences 10585 and 10588
Thursday 1 March 2018
8:00 AM - 10:00 AM
Location: Room 220B
Session Chairs:
John C. Robinson, KLA-Tencor Corp. (United States) ;
Ryoung-Han Kim, imec (Belgium)
Design-process-technology-co-optimization for manufacturability from a fabless perspective (Invited Paper)
Paper 10585-51
Author(s): William J. Miller, Qualcomm Inc. (United States)
Show Abstract
A model-based, Bayesian approach to the CF4/Ar trench etch of SiO2
Paper 10588-15
Author(s): Meghali J. Chopra, Sofia Helpert, Rahul Verma, Roger Bonnecaze, The Univ. of Texas at Austin (United States)
Show Abstract
Advanced combined overlay and CD uniformity measurement mark for double patterning
Paper 10585-52
Author(s): Boris Habets, Qoniac GmbH (Germany); Hsiao Lin Hsu, En-Chuan Lio, Charlie Chen, Jia Hung Chang, Sho Shen Lee, J.R. Yang, S.F. Tzou, United Microelectronics Corp. (Taiwan); Patrick Lomtscher, Stefan Buhl, Martin Freitag, Qoniac GmbH (Germany); Rex Liu, Qoniac Taiwan Ltd. (Taiwan)
Show Abstract
Using chip topography map data for quick and high accuracy CMP modeling
Paper 10588-16
Author(s): ChunLei Zhang, Semiconductor Manufacturing International Corp. (China); Zhengfang Liu, Cadence Design Systems, Inc. (China); Linda Wang, Jane Sun, Semiconductor Manufacturing International Corp. (China); Xin Li, Cadence Design Systems, Inc. (China); Kuanghan Chen, Brian Lee, Aaron Gower-Hall, Cadence Design Systems, Inc. (United States); Elaine Zou, Huan Kan, Semiconductor Manufacturing International Corp. (China); Tamba Gbondo-Tugbawa, Cadence Design Systems, Inc. (United States)
Show Abstract
Enabling optical metrology on small 5x5μm2 in-cell targets to support flexible sampling and higher order overlay and CD control for advanced logic devices nodes
Paper 10585-53
Author(s): Antonio Salerno, ASML Netherlands B.V. (Netherlands); Jacky Huang, Hong-Ming Kuo, Y.C. Wang, B.J. Cheng, K.S. Chen, H.T. Lin, Hy Lin, Taiwan Semiconductor Manufacturing Co. Ltd. (Taiwan); Ward Tu, Hammer Chang, Zack Hsu, Wei-Li Lin, ASML Taiwan Ltd. (Taiwan); Filippo Belletti, Adam Chuang, Isabel de le Fuente, Anagnostis Tsiatmas, Alok Verma, Vivien Wang, Hugo Cramer, Mariya Medvedyeva, Elliott McNamara, ASML Netherlands B.V. (Netherlands); Wade Huang, ASML Taiwan Ltd. (Taiwan); Daoping Li, ASML Netherlands B.V. (Netherlands)
Show Abstract
Session 6:
Pattern-based Analysis
Thursday 1 March 2018
10:30 AM - 12:10 PM
Location: Room 211
Session Chairs:
Lifu Chang, Qualcomm Inc. (United States) ;
Lars W. Liebmann, GLOBALFOUNDRIES Inc. (United States)
Pattern-based analyses for OPC verification of EUV and DUV based layers at 7nm
Paper 10588-17
Author(s): Piyush Pathak, Cadence Design Systems, Inc. (United States); Cyrus Tabery, ASML Brion (United States); Michel Cote, Frank Gennari, Ya-Chieh Lai, Philippe Hurat, Luca Matti, Cadence Design Systems, Inc. (United States); Chris Spence, ASML Brion (United States)
Show Abstract
Hotspot detection based on surrounding optical features
Paper 10588-18
Author(s): Yayori Abe, Fumiharu Nakajima, Masanari Kajiwara, Shigeki Nojima, Toshiya Kotani, Toshiba Memory Corp. (Japan)
Show Abstract
Range pattern matching with layer operations and continuous refinements
Paper 10588-19
Author(s): I-Lun Tseng, Zhao Chuan Lee, Yongfu Li, Valerio Perez, Vikas Tripathi, Jonathan Yoong Seang Ong, GLOBALFOUNDRIES Singapore Pte. Ltd. (Singapore)
Show Abstract
Combinational optical rule check on hotspot detection
Paper 10588-20
Author(s): Shumay Shang, Mentor Graphics Corp. (United States); Hongxin Zhang, GLOBALFOUNDRIES Inc. (United States); Rui Wu, Lianghong Yin, Alex Wei, Yuyang Sun, Mentor Graphics Corp. (United States); Shaowen Gao, GLOBALFOUNDRIES Inc. (United States)
Show Abstract
Pattern analysis and classification accelerates OPC tuning, monitoring, and optimization
Paper 10588-21
Author(s): Ruoping Wang, Paul Lupa, NXP Semiconductors (United States); Jason Sweis, Ya-Chieh Lai, Philippe Hurat, Cadence Design Systems, Inc. (United States)
Show Abstract
Session 7:
Advanced Patterning
Thursday 1 March 2018
1:30 PM - 3:10 PM
Location: Room 211
Session Chairs:
Chul-Hong Park, SAMSUNG Electronics Co., Ltd. (Korea, Republic of) ;
Lynn T.-N. Wang, GLOBALFOUNDRIES Inc. (United States)
IMEC N7, N5 and beyond: DTCO, STCO and EUV insertion strategy to maintain affordable scaling trend (Invited Paper)
Paper 10588-22
Author(s): Ryan Ryoung-Han Kim, Syed Muhammad Yasser Sherazi, Peter Debacker, Praveen Raghavan, Julien Ryckaert, Arindam Malik, Diederik Verkest, Jae Uk Lee, Werner Gillijns, Ling Ee Tan, Victor Blanco, Kurt Ronse, Greg McIntyre, IMEC (Belgium)
Show Abstract
Relaxing LER requirements in EUV patterning
Paper 10588-23
Author(s): Yandong Luo, Puneet Gupta, Univ. of California, Los Angeles (United States)
Show Abstract
Integrated manufacturing flow for selective-etching SADP/SAQP
Paper 10588-24
Author(s): Rehab Kotb Ali, Ahmed Hamed Fatehy, Mentor Graphics Egypt (Egypt); James Word, Mentor Graphics Corp. (United States)
Show Abstract
Comparison between traditional SADP/SAQP and selective-etching SADP/SAQP
Paper 10588-25
Author(s): Ahmed Hamed, Rehab Kotb Ali, Mentor Graphics Egypt (Egypt); James Word, Mentor Graphics Corp. (United States)
Show Abstract
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